Departamento de Engenharia Electrotécnica e de Computadores 
Guide to the study of MULTISTAGE DIFFERENTIAL AMPLIFIERS 
March 2004 
MULTISTAGE DIFFERENTIAL AMPLIFIERS 
Read the Instructions to know how you can better use this work. Know how it is organized and which navigation tools are available. See how you can complement the study with the simulation of some of the circuits presented here. 
See the table of contents of this work. The table is organized through a pop down menu revealed when you place the cursor over the titles. Through the Index you can directly access each one of the sections and exercises of this work. 
The main text of this work is enhanced with several complementary texts, in order to help the reader about matters not directly studied here. These are matters which are supposed to be studied before or later. Through the main text there are several links to these texts but you can also access them through the table of Annexes, organized in a similar way as the main Index. 
1. Introduction 
Operational amplifiers (OpAmps) with negative feedback allow highly versatile realisations, in particular highly stabilised gain amplifiers. In fact, today’s amplifiers are mostly utilised with feedback. 
Take the example depicted in fig. 1. This inverting amplifier has a voltage gain, v_{o} / v_{i}, very approximately equal to –R_{2} / R_{1}. To make this quantity a reasonable approximation it is simply required a very high open loop gain (i.e., A >> R_{2} / R_{1}, although it may vary significantly), a high input resistance (R_{i} A >> R_{2}), and a small output resistance (R_{o} << R_{2}). (Note: A, R_{i} and R_{o} are the OpAmp equivalent model parameters) 
fig. 1  Inverting montage 
Taking the basic BJTs or FETs amplifying configurations as reference, a natural question arises: How to realise an amplifier to attain such goals (i.e., that shows sufficiently high gain, high input resistance, and small output resistance)? 
From the set of basic single transistor amplifiers, the BJT’s common emitter (CE) topology [or FET’s common source (CS)] is the configuration that simultaneously allows the highest voltage gain with a R_{i} not too small. Thus, the amplifier above could be realised with a single transistor as indicated in fig. 2. Resistors R_{2} and R_{1} define the gain. By direct analysis, it can easily be shown that the gain is given by v_{o} / v_{i} @ 9,1 (verify it as an exercise), which is reasonably close to  R_{2} / R_{1} =  10. 
fig. 2  Common emitter configuration 
Nevertheless, it is notorious that the CE configuration, by itself, does not bring together the conditions to a satisfactory OpAmp characteristics. 
For example, it does not implement a differential input (consequently, the CE amplifier does not allow the noninverting implementation), it has a relatively small input resistance and a high output resistance (R_{i} @ r_{p} and R_{o} @ 100 kW // 10 kW). Inserting a resistor between the emitter terminal and ground will boost the input resistance. Yet, this procedure reduces the gain (and increases the output resistance, although marginally). Alternatively, FETs can be used at the input  at the cost of lower g_{m} and consequently lower gains. Nonetheless, no juggling will confer a symmetrical differential input to the CE topology. The solution resorts to a composed implementation (with more than one transistor) to obtain a differential input called the differential pair. Note, however, that other OpAmp characteristics should be searched for, such as: very high gain, high input and low output resistance, low voltage and current offsets. Simultaneously, one should not loose site for other characteristic improvements, such as band width and maximum slewrate. 
2. Differential pair 
Consider fig. 3 setting where a differential pair is implemented with two BJTs. If, v_{B1} = v_{B2} = v_{CM} (common mode voltage), the voltages v_{C1} and v_{C2} will not change even when v_{CM} varies (within certain limits set by the need to keep the transistors in active mode). On the other hand, if v_{B1} ¹ v_{B2}, the voltages v_{C1} and v_{C2} will no longer be equal. Thus, we may say that the differential pair (ideally) responds to differential signals (i.e., the input voltage difference) and rejects the common mode, i.e., does not react to identical signals at both inputs. 
fig. 3 – Bipolar differential pair 
2.1. Current variation 
2.1.1. BJT 
The total emitter current is kept constant by the current source I. Therefore, when the input differential voltage v_{D} = v_{B2} – v_{B1} changes in time, some of the current of a given transistor will be transferred to the other. This change in transistor current with input differential variation can be observed in fig. 4. 
The expression for the current can be found to be:
The differential pair operation is approximately linear for small differential input voltages. This corresponds to a region in the graph where the exponential exhibits an approximate linear behaviour. In fact, it can be shown that for v_{D} = V_{T} @ 25 mV, the gain changes about 20%. 
fig. 4 – BJT differential pair currents 
On the other hand, a ±100 mV input differential voltage is enough for almost all the current to be drawn by one of the transistors. 
2.1.2. FET 
The basic schematic is similar to a bipolar differential pair and is shown in fig. 5 (JFET example). The analysis is very similar to the differential bipolar case. Having in mind that:
naming and making we get:

fig. 5 – JFET differential pair 
This current changes as a function of v_{id} and is shown in fig. 6. The FET’s parameters used in this example is also shown on the graph. The main remarks, relatively to the bipolar differential pair, are, on one hand, the larger v_{id} value spread, and, on the other hand, the smaller characteristics slope around the origin. 
fig. 6 – JFET differential pair currents 
The MOSFET differential pair analysis (see fig. 7, where it is shown a MOSFET differential pair with enhancement MOSFETS – channel n) is not only similar to a JFET, but also the same conclusions are driven. 
In fact, the MOSFET current function is the same of the JFET, however is commonly written in a different form as:
Consequently, the current versus v_{d} is the same, however with a different form:

fig. 7 – MOSFET differential pair 
2.2. Small signal operation 
Take the BJT differential pair as reference. If around v_{D} = 0 we find: we get An alternative point of view to get the same result is to observe fig. 8 schematic for small signals. The input differential resistance is R_{id} = 2 r_{p}, because looking into the base of any transistor we see r_{p} + (1+b) r_{e} = 2r_{p} . 
Having in mind, for example, that:
for the three possible outputs the following differential gains result:

fig. 8 – Small signal operation 
This last gain corresponds to an amplifier with differential signals both at the input and output (fig. 9). There is another way to look into this problem: If we consider the amplifier as an ideal differential amplifier (where essentially the common mode gain is null), according to fig. 10 circuit, the response to a signal v_{i} can be analysed with the base of T_{2} connected to ground: The collector of T_{2} does not influence T_{1}. This last transistor is in common emitter configuration with an emitter resistance R_{E} equal to r_{e2} = 1/g_{m2}. Then, the gain is approximately:
However, if the other output is intended, it is enough to think that both collector currents (signal) are necessarily equal, and, consequently, the gain will be symmetric of the indicated above. Nonetheless, it is called the attention upon the fact that this configuration corresponds to a variant of a circuit known as cascode that it will be studied ahead. 
fig. 9 – Differential input and output amplifier
fig. 10 – Alternative method for evaluating the differential pair gain 
A small signal analysis can also be done taking the equivalence between the differential pair and the CE configuration.
Even assuming that the biasing source is not ideal (see fig. 12), in rigorous terms and in differential operation, i.e.,
v_{B1} = v_{d} / 2 and v_{B2} =  v_{d} / 2,
the common node at the emitters can be represented by a virtual ground, where a transistor “gets” a
+ v_{d} / 2 signal and the other a  v_{d} / 2. Thus, each transistor is
equivalent to a CE configuration with a grounded emitter, as shown in fig. 13.

From fig. 13 we get:
or, if transistor’s r_{o} cannot be ignored:
Since A_{d1} = v_{c1} / v_{d} it results: 
fig. 12 – Non ideal biasing source
fig. 13 – Equivalent CE montage

and, naturally, A_{d2} =  A_{d1} e A_{dd} = 2 A_{d1}. A similar analysis can be performed on a FET differential pair. The sole relevant difference is the linear operation span which is significantly bigger in a FET differential pair. It may reach some volts while a bipolar pair is restricted around ± 25 mV. Thus, we get: , and If it is not possible to ignore r_{o}, we have to change R_{D} by the parallel R_{D }// r_{o}. 
2.3. Common mode operation 
The common mode operation is illustrated in fig. 14. Due to symmetry and to the equality v_{B1} = v_{B2}, half circuit analysis is sufficient, as shown in fig. 15 (note that, for common mode signals, resistor R can be substituted by two 2R resistors, in parallel, which allows us the analysis of each transistor in separate). 
fig. 14 – Common mode operation fig. 15 – Common mode equivalent CE montage 
If R_{C} « r_{o}, we get: and by analogy and The common mode rejection ratio is, by definition,
such that, for each unique output (v_{c1} or v_{c2}), we get . 
For the differential output CMRR = ¥, obviously except the case where the symmetry is not perfect. Verify that, for example, if R_{C1} = R_{C} and R_{C2} = R_{C} + D R_{C}, we get:
Fig. 16 illustrates a common mode input resistance definition. Considering only halfcircuit, the resistance seen by v_{CM} is 2 R_{iCM} . 
fig. 16 – Common mode input resistance 

2.4. Operation with arbitrary input voltages 
It is convenient at this stage to (re)introduce the input signals decomposition issue, v_{B1} and v_{B2},
into two new variables: Evidently, this conveys into v_{B1} = v_{CM} + v_{D} /2 and v_{B2} = v_{CM} – v_{D} /2. Let v_{1} and v_{2} be the signal components of v_{B1} and v_{B2}. In general, the differential pair input voltages, v_{1} and v_{2}, corresponds neither to a differential nor to a common mode. 
fig. 17 – Input signals 
From what was said above, we have: and The output can be expressed as v_{o} = A_{1 }v_{1} + A_{2}v_{2} as long as the signals magnitude is such that linear operation can be considered, which can further be manipulated into: We will have then A_{d} = (A_{1} – A_{2})/2 and A_{cm} = A_{1} + A_{2}. Rewriting v_{o} expression we get:
(where CMRR is expressed in nonlogarithmic form) which then shows that, if the CMRR is sufficiently high, the output signal depends solely on the input differential component. Because the desirable operation is precisely this, the term
constitutes the error of the differential circuit model. 
2.5. Other nonideal characteristics 
2.5.1. Input offset voltage 
If the differential pair is perfectly symmetric, with the output voltage taken between the two collectors (or two drains) and connecting both inputs to the ground, then v_{O} = 0. Because perfect symmetry is impossible, in fact v_{O} ¹ 0 is verified. Thus, an input offset voltage can be defined as:
The asymmetry can result from the load resistor and/or, transistor characteristics dissimilitude. If the load resistors differ by DR_{C} (or DR_{D}), that is, if or results for the BJT pair: and for a MOSFET pair: The relevant transistor characteristics responsible for input offset voltage, are the reverse saturation current I_{S} for the BJT case, and the K factor (or I_{DSS}) and the threshold voltage V_{t} (or V_{P}) for FETs case. Thus, for a BJT pair, the offset result is:
and for a MOSFET pair: and respectively. 
2.5.2. Bias current and input offset current 
Given its very small values, input currents are nonrelevant for the FETs differential pairs. Consequently we will only consider the case of a BJT differential pair. In a symmetric pair, the input currents at rest are equal to:
This common value is called the input bias current (I_{B}). Due to the inevitable input asymmetry, the bias currents are in fact different. This difference is called input offset current.
In particular, if transistor gains b differ by Db, the offset is:
Up to here we have indicated a symbolic current source to bias the differential pair. It maters now to see how can that current source be realised. Discrete circuits are going to be distinguished from integrated current source circuits. 
3. Bias circuits for differential pairs 
3.1. Discrete circuits 
A discrete component typical constant current source (CCS) realisation is illustrated in fig. 18 for a BJT case. A practical example will allow us an easier router to evaluate and project CCS circuit. We will assume V_{BB} = 12 V and –V_{EE} = 12 V, and that I_{C} = 1 mA is needed. Suppose that the transistor has a b = 100 and V_{A} = 100 V. Taking V_{B} = 8 V, for I_{E} @ 1 mA, results R_{3} = 3.3 kW. Then, assuming I_{B} @ 0, we get: 
fig. 18 – Discrete differential pair 
and R_{1} = 5 R_{2} Choosing a current at R_{1} and R_{2} as being approximately 10% of I_{C}, (so that I_{B} can be neglected) we get: then R_{2} = 40 kW and R_{1} = 200 kW. 
3.2. Integrated circuits 
The resistor values required by the previous setting are impractical for integrated circuits. On the other hand, good matching transistors are easy and economic to fabricate. Furthermore, integrated circuits using exclusively MOS technology (in particular CMOS) really excuse the use of resistors. 
This way, a common technique utilised in integrated circuits to realise CCS is the current mirror. The basic current mirror with MOSFET is shown in fig. 19. If both transistors are exactly matched, and since V_{GS} is the same for both transistors, their currents will be equal. In fact, taking into account the channel length modulation, this equality is only verified if V_{DS2} = V_{DS1} = V_{GS}. This way, the mirror’s output resistance, r_{o2}, is a quality parameter. If both threshold voltages are the same, but different K factors are used, then 
fig. 19 – MOSFET basic 
and results in:
This expression shows that ratios different from the unit transfer current I_{O} / I_{REF} ratio are attained by a simple actuation over the transistors’ geometry. 
The basic BJT current mirror configuration is shown in fig. 20, where:
Assuming T_{1} º T_{2}, neglecting the effects of b and r_{o}, and since V_{BE1} = V_{BE2}, results I_{O} = I_{REF} . 
fig. 20 – BJT basic current mirror 
If the effect of b is taken into account, it is easily verified that:
which shows that the error is made smaller with bigger b. Simultaneously, when used as a CCS the circuit’s output resistance is only r_{o}, a value that can be insufficiently high. Hence, the modifications usually made to the basic current mirror aim to overcome the limitations resulting from finite b and r_{o}. The use of an extra transistor (T_{3}, in fig. 21) or the use of Wilson and Widlar configurations, shown in figs. 22 and 23 respectively, are ways to improve the referred characteristics. 
fig. 21 – Base current compensation 
fig. 22 – Wilson’s mirror 
fig. 23 – Widlar’s source 
The current mirrors output resistance made with MOS can also be increased using Wilson or cascode configurations. 
4. Improving the bandwidth 
Recall that the amplifier bandwidth refers to the frequency range within which the gain remains almost constant. We call (lower and upper) cutoff frequencies to those range limits. The criterion utilised to define these frequencies corresponds to the measure of the point where the maximum gain decreases by 3 dB, i.e., about 30% gain value decrease (3 dB means halving the electric power, which from the voltage point of view corresponds to 1 / @ 0.707). At the lower limit, i.e., at low frequencies, capacitive coupling utilisation is responsible for the gain. So, when direct coupling is used, such as with integrated OpAmps, usually there is no gain decrease at low frequencies, accordingly the lower cutoff frequency is zero. However, at high frequencies, due to transistor’s intrinsic capacitive effect the gain decrease is unavoidable. Otherwise infinite frequencies would imply electrons (or other carriers, such as holes in p type semiconductors) infinite accelerations, and therefore infinite forces would be present, which are obviously impossible in Nature. The upper cutoff frequency depends not only on the transistors characteristics and quiescent point but as well on the chosen circuit configuration. Then, in a direct coupling amplifier, the bandwidth coincides with the upper cutoff frequency. 
4.1. CE configuration bandwidth 
The CE behaviour at high frequencies is of special interest to study the differential pair, because, as we have seen before, the differential pair is somehow equivalent to a CE montage. From the three basic configurations, it is precisely the CE that has the smallest bandwidth, i.e., it has the smallest upper cutoff frequency. The reason for this poorer behaviour at high frequencies can easily be found through a simplified analysis of the high frequency equivalent circuit of fig. 24, where r_{o} was ignored and, for the sake of simplicity, we have also omitted the base biasing mesh. 
fig. 24  CE high frequency equivalent circuit 

Part of the answer, indicated in Exercise 5, can be obtained in a simplified manner with the help of Miller’s theorem to the C_{m} capacitor, considering the midband gain value (A_{MF} ). 

fig. 25 – Midband gain and first pole 
Thus, the resulting schematic (fig. 26) is valid only to determine the bandwidth (w_{H} @ w_{p1}), and not the frequency response in total. Besides, it is notorious that the zero disappears in this analysis. From fig. 26 we get , and 
The K value is easily obtained: 

Then, the time constants associated with both independent capacitors are: and with and corresponding poles and Since in general, w_{1} << w_{2}, the band limit may be considered coincident with w_{1} :
On the other hand, the middlefrequency gain approximation used does not allow the identification of w_{2} as the second pole of the original circuit. A more accurate estimation for the first pole and also for the second one can be obtained, although more onerously, using the time constants method. Note, as reference, that C_{p} and C_{m} have typical values in the order of tens and unities of pF, respectively. Besides the fact that C_{m} is small, its actual contribution is large because the capacitor value is multiplied by the configuration gain. This is known as the Miller multiplicative effect. Let us make a reference to the zero. In fig. 24 schematic, the output voltage is annulled when the C_{m} capacitor current is equal to the current source current, i.e., when the current in R_{C} is zero. Then,
This is the frequency of the zero, which coincides with the calculated value in Exercise 5. However, one should note that, given the capacitor values and assuming g_{m} in the order of 100 mA/V, the zero will be situated at a frequency much higher than the poles. At the present point this does not seem of great importance however, attention should be called upon the fact that the zero is located on the right hand side of the S plane (it is real and positive). Unexpectedly, this zero introduces a phase delay and not a delay advance. In this perspective behaves as a pole on the left hand side of the S plane. In the common base and common collector configurations the Miller multiplicative effect does not exist. The last has the C_{p} capacitor between two nodes with slightly less than one positive gain, and the former has both capacitors to ground: the Miller effect is then out of the question. In this way, both configurations present much higher upper cutoff frequencies. It is known that in a given configuration the gain bandwidth product is approximately constant  if the gain increases the bandwidth diminishes. From all considered configurations, only the CE configuration shows both bigger than one current and voltage gains. The CC configuration has unit voltage gain and BC has a unit current gain. Thus, in a certain way, it is “natural” that the existence of two large gains make the bandwidth diminish. From this analysis results a relatively poor high frequency behaviour for the CE configuration (thus, also for the differential pair), which needs to be improved. One configuration with a CE equivalent voltage gain but larger bandwidth is the cascode pair. 
4.2. CECB Cascode pair 
Fig. 27 (a) represents a biasing scheme for the cascode pair and in (b) the equivalent circuit for signals, where R_{B} = R_{1} // R_{2}. 
fig. 27  CECB cascode pair; (a) bias circuit; (b) small signal equivalent circuit 
which insights that an equivalent CE v_{o} / v_{i} gain can be built with an equal transistor biased at the same DC operating point. However a difference is in favour of the cascode configuration. In fact, a large R_{C} is adopted when a large gain is needed. If R_{C} is sufficiently large, the r_{o} >> R_{C} approximation may no longer be acceptable. Then for a CE we should consider:
If R_{C} >> r_{o}, the maximum gain is given by – g_{m} r_{o}. 
To examine what takes place with the cascode configuration, let us determine G_{m} and R_{o} relatively to the equivalent model of fig. 27 (a) and represented in fig. 28. Calculating G_{m}, gives: 
fig. 28  Cascode pair equivalent circuit 
To calculate R_{o}, fig. 29 is used. 
fig. 29  Evaluation of output resistance R_{o}; (a) Deactivating the independent sources; (b) Circuit simplification 
A deactivation condition was imposed to the independent sources in fig. 29 (a), which annuls the fonte g_{m1} v_{p1} current source. Given that r_{o1} >> r_{p2} , then the parallel is approximately r_{p2} . Finally, applying the Thévenin’s theorem results in fig. 29 (b) schematic, where the output resistance can immediately be found to be:
where it was considered r_{o} = r_{o1} = r_{o2} (equal transistors with the same operating point). Then for the voltage gain we get:
Hence the maximum gain value will be – g_{m} b r_{o} , which is considerably larger than the common emitter gain. As mentioned above, the cascode bandwidth is larger than the equivalent common emitter. Let us check why with a simplified qualitative analysis. The cascode second stage is a common base amplifier, which frequency response is very good. So, it is the first stage, a common emitter, that will primarily condition the high frequency response. The CE lower cut off frequency results from the Miller multiplicative effect over the C_{m1} capacitor. However, because the first stage load is the second stage low input resistance (r_{e}), the Miller multiplicative factor will be solely:
This way, the upper cutoff frequency of the circuit will be considerably larger than the upper cutoff frequency of a CE. 
4.3. CECB complementary cascode 
Fig. 30 (a) represents the biasing scheme of a complementary cascode pair and in (b) the equivalent circuit for signal analysis. 
fig. 30  CECB complementary cascode; (a) Bias circuit; (b) Small signal equivalent circuit 
This configuration utilizes a npn and pnp transistors, which signals equivalent model is the same as last configuration (the noncomplementary transistor cascode). Hence, the schematic of figs. 28 e 29 apply here. Recall the fact that nothing changes in terms of signal functionality whichever the transistor is pnp or npn. The sole change relates with the need for a dc current to source the collector of T_{1} and the emitter of T_{2} simultaneously. The change to the signal circuit parameters is minimal and negligible since the resistance associated with the current source is generally much larger than r_{e2} with which will be in parallel to ground. However it may happen that I_{E1} ¹ I_{E2} which can lead to different parameters for both transistors. Regarding everything else, all the reminding signal analysis is then still valid. This configuration presents another advantage of great interest to the multistage amplifiers architecture, such as the case of OpAmps: the displacement level between the input and output, observed in the canonical cascode, can be annulled. In fact, this last presents a displacement level of: , while the complementary cascode is solely: 
4.4. CCCB complementary cascode 
This configuration utilizes a npn and pnp transistors, which signals equivalent model is represented in fig. 31. Assuming transistors with identical characteristics, biased at the same static operating point, the analysis leads to:

fig. 31 – CCCB complementary cascode – 
then , that is, the gain is positive (noninverting circuit) with half a value of the CECB cascode gain. However, note that in compensation the input resistance doubles the CECB cascode input resistance value: . Let us calculate now the maximum gain possible. The G_{m} calculation is trivial and leads to: . Fig. 32 will be utilised for the R_{o} calculation. Two essential steps to find the output resistance of fig. 31 circuit, using the circuit transformations method, are represented in fig. 32. It is assumed that the source resistance, R_{s}, is negligible in face to r_{p1} . If this is not true, r_{p1} needs to be replaced by R_{s} + r_{p1} , which will result in a slightly larger output resistance. Thus, the value found bellow should be faced as a lower limit of a more general output resistance value. 
fig. 32  Evaluation of output resistance R_{o}; (a) Deactivating the independent sources; 


Concerning bandwidth, one might evaluate it in a simple way. Note that capacitor C_{m1} is connected to the ground, as well as C_{p2} and C_{m2} (see fig. 33). On the other hand, capacitor C_{p1} connects two nodes with a gain that can easily be found to be ½. 
fig. 33 – Capacities in the CCCB montage 
This gain is independent of frequency and means that the Miller’s theorem can be applied rigorously, i.e., without the usual restriction that results from the approximation to the midband gain. In this way, the following fig. 34 schematic results. 
fig. 34 – CCCB montage equivalent circuit applying Miller’s theorem to C_{p}_{1} 
Since  C_{p1} and C_{p2} annul each other, the circuit only presents two independent capacitances, which time constants are: and Which corresponding poles will be dominant or, at least, which will have the lowest frequency, is dependent on circuit parameters. However, it is notorious that any of them occur at a higher frequency than the common emitter and even higher than the CECB configuration. One might reach this conclusion qualitatively. In reality, the CCCB configuration is made of two stages, both with very good high frequency responses. In particular, the first stage, a common collector, has a upper cutoff frequency larger than the lowgain common emitter, such as the case of the CECB cascode. Equally the second stage is a common base with a very high cutoff frequency. 
4.5. Cascode differential pair 
The good frequency response properties found in a complementary cascode are utilized in the differential pair cascode, which schematic can be seen in fig. 35. This configuration is used as an input stage, e.g, in the 741 OpAmp. 
fig. 35  Differential cascode pair; (a) Simplified bias circuit; (b) Small signal equivalent circuit 
To find the voltage gain note that: then and from which we conclude that the gain is half of that one found in a simple differential pair. On the other hand the input resistance is double: . The use of a cascode differential pair improves the general characteristics of the pair, although it seems to reduce the gain. Note, however, that the maximum gain limit is the same of a simple differential pair. This discussion about the gain raises a question about the gain allowed by the differential pair and if it is sufficient to attain the typical values presented by a general purpose OpAmp. 
5. Maximising the differential pair voltage gain 
Consider the simple differential pair with single output (fig. 36) as reference. The open circuit differential gain, as seen before is:
The use of large value passive resistors are not practical so, in general, R_{C} << r_{o}, then:

fig. 36 – Evaluation of the basic 
5.1. Differential pair with a simple active load 
The gain can be considerably increased if an active load is used instead of a passive one, i.e., a current source setup with output resistance R_{o} , which, as seen before, can be several times larger than r_{o} (fig. 37). The analysis leads to a gain value of:
Thus, for example, if R_{o} = 4 r_{o}, we get:


5.2. Differential pair with current mirror active load 
A larger value for the gain can be obtained if a current mirror is used as load, like fig. 38 shows. The mirror effect leads to:
and if r_{o2} = r_{o4} = r_{o} comes: which is larger than what can be found with a simple active load. This value can be further improved using a mirror with higher output resistance (fig. 39). 


Either using the Widlar’s symmetric mirror (fig. 39 (a)), or the base current compensation mirror (fig. 39 (b)), we get:
being r_{o2} = r_{o4} = r_{o}, because R_{o4} > r_{o} , then: For example, if R_{o4} = 4 r_{o} , then: 
Hence, we may conclude that the open circuit maximum gain (it lowers with the load), is in the order of g_{m} r_{o} / 2 (it might only be slightly larger). Since
then, for example, if we consider V_{A} = 100 V, comes:

Although it might be raised by a small amount, this value is well bellow the usual tens or hundreds of thousands gain values characteristics of OpAmps. Even independently of other considerations, such as the ones relative to the output resistance, it is clear that a differential pair is insufficient to realize an amplifier with OpAmp like characteristics. A second stage (at least) is needed to attain the desired gain level. The second stage needs to have a reasonable large value of gain (at least some tens) and a large input resistance to avoid gain degradation of the first stage amplifier. A low output resistance, as it is required by an OpAmp structure, is also desirable. Note however that this stage does not need to have a differential input. 
5.3. One CMOS differential pair with active load 
Fig. 40 shows an example of a CMOS differential pair with active load. The output dc voltage is, normally, established by the next stage as can be seen in the OpAmp internal circuits. The circuit is analogous to the bipolar version. Thus, the current signal is: where The output voltage is: With 

the voltage gain comes: To get high gains, one differential cascode and one cascode current mirror can be used. However, this lowers the output signal excursion possible.
The use of FETs is specially interesting because of the very high input resistances that is allowed to get. The offset voltage is in the same order (some milivolts) of the bipolar differential pairs but, the bias currents at the input are much smaller than what is possible to make with bipolar transistors. The major FETs inconvenience is the low transconductance and, consequently, the lower larger gain possible. Nowadays, integrated OpAmps are fabricated using CMOS technology. The general characteristics are good and very low power voltages (1 V!) can be used with very low power consumption. 
6. High voltage gain and input resistance stages 
6.1. The Darlington pair – CCCC configuration 
Let’s consider the circuit of fig. 41, where the biasing components are omitted. If we suppose that T_{1} º T_{2} and that they are equally biased, let’s compute the voltage gain and input resistance:


that leads to If b » 2, we have:
which is the same expression we get for the single transistor emitter follower. But the input resistance, if b >> 1 and R_{E} >> 11/g_{m} is: much larger than the value b R_{E}, that is the approximate value we get for a single transistor. In the same way, the shortcircuit current gain is (b +1)^{2} much larger than (b +1) that the single stage has. Finally, the output resistance is the same in both cases (1/g_{m}), if the first base is connected to ground. Probably, the most interesting result is that the two transistor montage can be seen as one only transistor where the three terminals (B, C, E) are respectively, the first base, both collectors and the second emitter and displays a large current gain, typically b ^{2}. However, this is not completely true because in general the two transistors are very different being common that the first is a high b small signal transistor while the second is a low b power transistor. 
6.2. Common Emitter Darlington configuration 
In spite of what has just been said, we will admit, for the sake of simplicity, that both transistors have the same characteristics and biasing point. Then, let’s consider the schematic of fig. 42. Input resistance:
Voltage gain: 

We may conclude that this circuit has approximately the same voltage gain as a simple CE, but a much larger input resistance (b times larger). However, as the internal ouput resistance is halved (r_{o} / 2), the maximum possible gain is smaller than what we can get with one only transistor. Therefore, this circuit has the required characteristics for the intermediate stage of an OpAmp. However, the high frequency response is deficient. In fact, C_{m} of T_{1} is subject to a very strong Miller effect. 
6.3. CCCE configuration 
Fig. 43 represents the CCCE circuit and its small signal equivalent. This is very similar to the circuit we just analysed (the Darlington montage) except for the fact that the two collectors are not connected. 

Again, for the sake of simplicity, we will admit that T_{1} and T_{2} are equal and equally biased. Input resistance:
Voltage gain:
and

This circuit presents the same gain and input resistance as the CE Darlington transistor. However the maximum voltage gain is twice as large, since the output resistance (r_{o}) is doubled. Though, the most significant change concerns the bandwidth. As the first stage (CE) has a good high frequency response, as we have seen before, and the Miller effect upon C_{m} of the second transistor does not limit much since it is charged by the low output resistance of the emitter follower the frequency behaviour of the circuit is quite good. This is why this montage is quite common in the intermediate stage of general purpose OpAmps. We have been referring to the common configurations of general purpose OpAmps. In general they still have a last stage that should satisfy two requirements: to have a high input resistance not to degrade the voltage gain of previous stages and have a low output resistance to be able to drive the output load. The voltage gain does not need to be high, since the two previous stages are able to provide it. Therefore, these are the characteristics we expect to find in an emitter follower circuit. 
7. Output stages 
The basic emitter follower presents the characteristics we have previously referred to as being desirable for an output stage but has a serious drawback: it has a very low efficiency which is important when we are dealing with power stages. In fact, the active devices in this circuit, as in all the others that we have studied so far, are always active for the whole excursion of the input signal (the whole period, if the signal is periodic): this is what we call the Class A behaviour (as opposing other situations in which the devices can be cutoff during part of the period). Class A has the advantage of presenting the smallest distortion but its maximum efficiency is only 25%, as we will see later on, although in certain special configurations it can be improved up to 50%. This low efficiency is very inconvenient for the output stage in power amps once the main power dissipation is precisely in the output stage. This is why the output stages are normally projected to work in Class B where the transistors are active, for a sinusoidal signal, during half period. This enables the efficiency to be increased to a value close to 78.5% (p/ 4 ´ 100%). Naturally, a circuit with only one transistor working in class B would increase the distortion in such way that it would be more or less useless. We will see how to minimize the distortion. The transistors can still function in other classes of which we shall now refer two:

7.1. Voltage follower complementary pair 
The typical configuration used in OpAmp output stages is a voltage follower pair that uses complementary transistors, symmetrically connected. Each transistor works in class B but the way they are connected assures that there is a continuous current flow in the load. Although this configuration may appear with slight differences, the schematic shown in fig.44 is very typical. To understand how this circuit works, we will start with an idealized version for the components. 

7.1.1. Ideal situation 
Let’s consider the circuit depicted in fig. 45 where T_{1} and T_{2} are identical, except for the fact that one is npn and the other pnp. We shall suppose that the continuous value V_{I} of v_{I} is such that V_{O} = 0 and that the transfer characteristics of both transistors are identical (see fig.46). When v_{i} = 0 both transistors are cutoff (i_{c1} = i_{c2} = 0) and therefore i_{O} = i_{o}= 0 and v_{O} = v_{o} = 0. 

Since i_{O} = i_{C1} – i_{C2} a current will always flow in the load. Provided that none of the transistors goes to saturation, the output will be a replica of the input. Bearing in mind that and , both voltages will have a sinusoidal variation identical to v_{O} around the mean value V_{CC}. Fig. 47 shows the relevant voltage and current waveforms. 


It is thus clear that this special configuration will allow, in the ideal case, that the circuit behaves like a voltage follower, although each transistor is in Class B, being cutoff for half of the cycle. Due to the alternate conduction of the transistors, this configuration is also known as pushpull. 
7.1.2. Circuit behaviour with real components 
For the real circuit the situation is different: it is necessary that v_{BE} gets above a certain value V_{g} (about 0.55 V for low power Si transistors) so that the collector current becomes significant. We shall take, to make the analysis simpler, a piecewise approximation to the characteristic, as shown in fig. 48. Under these conditions, the transfer characteristic of the follower pair will have a dead zone as in fig. 49. 


As a consequence, under a sinusoidal regime, the output will not be a sine wave, having a strong distortion around zero, known as the crossover distortion (fig. 50). 

In order to reduce it, both transistors should be at cutin for a zero voltage input. To be precise, in this situation the transistors are in Class AB but so close to class B that the efficiency is only slightly smaller than in class B. 
7.1.3. Compensating the crossover distortion 
There is a number of possible solutions to bias the follower pair at cutin. One of the more popular and versatile ones is the so called V_{BE} multiplier (fig. 51). If the base current of T_{3} is much smaller than the current in R_{1} and R_{2},
Through the choice of R_{1} and R_{2} we can obtain the desired value for V. 

A different version of the V_{BE} multiplier, frequent in IC OpAmp circuits (namely in the very common 741) is depicted in fig. 52. 

7.1.4. Understanding the V_{BE} multiplier 
We have seen that the role of the V_{BE} amplifier is to suply the biaising voltage to the output transistor pair, i.e. the role of a constant voltage source. This role is better played if the resistance seen between the multiplier terminals is very small. This means that, from a signal point of view, the two bases are shortcircuited. Let’s now compute its value for the circuit of fig. 51. The equivalent circuit to compute the resistance value is given in fig. 53. 

The value of the resistance is
and its evaluation is left as an exercise. With the values given for Exercise 7 the result is R_{o} @ 432 W. This is a small value when compared with r_{p} for transistors T_{1} and T_{2}. 
So, it is an acceptable approximation to consider the V_{BE} multiplier as an ideal constant voltage source and the voltage follower pair behaves like a simple emitter follower and so its voltage gain A_{v} @ 1 and R_{i} = r_{p} + (b + 1) R_{L}. In fact, the situation departs from this ideal result mainly because the output stage has frequently to handle large signals which means that both the voltage gain and the input resistance vary significantly along the signal swing, because both r_{p} and b are a function of the collector current. However, as the input resistance variation affects the voltage gain of the preceding stage in the inverse sense, the change of r_{p} is fairly compensated; there remains the variation of b but this is normally much less significant. Cascading the three stages that we have analysed (the differential pair, the high voltage gain stage – e.g. CCCE – and the voltage complementary pair, we obtain a complete amplifier that has the necessary characteristics to build an OpAmp (fig. 54). 

However, one of the characteristics that we have only scratched is the input resistance that should be high for each stage that we analysed. In the following chapter we will go further in this respect. 
8. Getting a high input impedance 
Let us start by reviewing some basic transistor configurations that can lead to high input impedance. The BJT CE as well as the FET CG configurations are to be excluded, due to the fact that R_{i} is inevitably low (@ 1/g_{m}). In the remaining configurations, when there is the gate of an FET as input terminal, R_{i} is very high but, due to a smaller g_{m}, the FETs, in general, display a smaller gain. The CC configuration presents a high input resistance but a unit voltage gain. Therefore, whenever we need a higher voltage gain it is frequently associated to a CE. The CE configuration with an emitter resistor has also a higher R_{i} and a moderate voltage gain and it is sometimes a useful montage when the circuit requirements are not very demanding. Among the configurations we have been seeing to behave as input stages with moderate gain, in the CE configuration, R_{i} equals r_{p}. Having a differential pair increases it to 2 r_{p} and even with a differential cascode it is at most 4 r_{p} . Is this enough? 
8.1. The CE input resistance 
The value of r_{p} is
which means that its value depends upon the collector current. If we keep I_{C} low enough, r_{p} can be fairly high. Let’s take as an example b = 200 and I_{C} = 10 mA, and we will have:
If we have a differential pair in which both transistors have the above static values, R_{id} = 1 MW. We should bear in mind that we have always ignored r_{m}. That can be done if R_{L} is not very large. However, if we want to have very high voltage gain, R_{L} may be very large and r_{m} may have to be considered. Take the example of fig. 55 to evaluate R_{i}. 
fig. 55  Evaluation of the common emitter input resistance 
The value we get is which is left to be obtained as an exercise. In any case because g_{m} R’_{L} is high. Indeed, if for instance I_{C} = 10 mA, V_{A} = 100 V, b = 200 and R_{L} is high, close to r_{o}, g_{m} R’_{L} = 2000. Then It can be shown that r_{m} ³ b r_{o} and for modern IC BJTs, r_{m} @ 10 b r_{o}. Taking again, for simplicity, R_{L} = r_{o}, we get: 
and so, 
and 
We may conclude that when we have a very high gain, the Miller effect over r_{m} may reduce the input resistance by an appreciable amount. It should be stressed, however, that this effect is not present in other configurations, namely in the cascode. 
8.2. Decreasing the input resistance of the emitter follower due to the base biasing 
The topic that we will now discuss is not much relevant in integrated OpAmps, where the biasing scheme is normally obtained with current sources and current mirrors. In discrete circuits, however, circuits are commonly biased through voltage dividers. Let’s consider the circuit in fig. 56, where T is a simple transistor but which, in other circuits, might be a Darlington configuration. 

The transistor input resistance, R_{iT} , is and may be very high. For instance, if b = 100, I_{C} = 1 mA and R_{E} = 10 kW, we will have: However, the “real” input resistance for the circuit is: which means that to have R_{i} @ R_{iT} , we have to choose R_{B} >> R_{iT} . If, for instance, R_{B} = 10 MW, R_{1} and R_{2} had to be extremely large and the Thévenin voltage
would have quite an unusual value! Let’s now consider the circuit of fig. 57(a) as well as, in fig. 57(b), its small signal equivalent, where R_{B} = R_{1} // R_{2}. 

Applying the Miller’s theorem to R_{3} we get the result depicted in fig. 58, where A_{v} is the voltage gain, slightly smaller than one, i.e., . Therefore will be very high and R_{i} @ R_{iT}. 

This effect, when A_{v} ® +1, is known as bootstrap. It should also be noted that the value of the gain and the input resistor should take into account that the effective emitter load is not only R_{E}, but also R_{B} and . This last value is also very high and ... negative! Let’s now recall that when we have the parallel of R, a finite and positive resistance, with R’, which may vary from ‑¥ to +¥, its value varies according to fig. 59. 

So, as R_{E} // R_{B} has normally a moderate value, its parallel with a very high negative resistance is only slightly larger than R_{E} // R_{B} . We should also note that positive and negative resistance is quite normal if we are talking of dynamic values or impedance instead of resistance. An infinite impedance is obtained, for instance, with a parallel resonant L / C circuit, which is an illustration of this if we take Z instead of R. By bootstrapping the biasing resistors we achieve a very high input resistance, similar to the one we see at te base of the emitter follower. 
It is interesting to see how far can we go in increasing the input resistance. If R_{E} is the emitter resistor, we have the circuit of fig. 60.
We can then write 

From the preceding analysis we can draw a number of conclusions concerning the procedure to adopt to achieve a high resistance at the differential input of an amplifier with a typical OpAmp structure:



9. Analysis of a typical three stage OpAmp (mA741) 
One of the most typical three stage bipolar OpAmps is certainly the mA741 developed by Fairchild but produced, today, by a large number of different brands. It is a generalpurpose high gain OpAmp, useful for low frequency applications. Its internal architecture displays most of the conventional IC stages that we have been studying. The first stage is a differential pair using complementary cascode montages (T_{1} to T_{4}) having as an active load a npn current mirror with base current compensation (T_{5} to T_{7}). 

The CCCB cascode configuration provides a large bandwidth with small input capacitance. The input resistance is also higher (approximately the double) than what would result from a simple differential pair with identical bias currents.The intermediate stage uses a CCCE montage (T_{16} to T_{17}) having high input resistance, high gain and a good frequency response. The 30 pF capacitor connected between input and output of this stage provides, as will be seen later on, a Miller (pole splitting) compensation, guarantying an unconditional stability. The output stage has the adequate high input resistance and low output one as well as good current source and sink capacity. In this way, the fundamental cell of this stage is the emitter follower complementary pair (T_{14} to T_{20}) with crossover distortion compensation (T_{18}, T_{19} and R_{10}). This stage is preceded by another single transistor CE (T_{23}) that is used as a buffer between the second and the output stages. Circuit bias currents are, as usual, provided by a set of current mirror configurations. T_{11}, T_{12} and R_{5} establish the value of the current that is mirrored by T_{10}. The connection to the base of T_{3} and T_{4} and the T_{8}T_{9} mirror, establish the currents in the differential pair through a feedback loop. The reference current is also mirrored from T_{12} to the double collector transistor T_{13} which can be seen as two independent transistors T_{13A} and T_{13B}. The 741 OpAmp has still a set of extra transistors (T_{15}, T_{21}, T_{22} and T_{24}) the role of which is to protect the device from damaging output short circuits. Terminal A and B are used for offset compensation, by means of a 10 kW potentiometer connected between A and B and the middle point connected to . In the remaining analysis, we will take, for all the transistors (except T_{21}, T_{22} and T_{24} that have a three times larger area), I_{S} = 10^{14}A. The total area of T_{3} is still the same but split unevenly between the two components: three fourths to T_{13B} and the remaining fourth to T_{13A}. Therefore I_{S13A} = 0.25 ´ 10^{14} A and I_{S13B} = 0.75 ´ 10^{14} A.
Furthermore, we will take, for npn transistors, Finally both for DC and AC analysis, although we only look at the internal circuit, we will always admit that a negative feedback loop is closed so that the DC output voltage is essentially zero and all the transistors are in the active region. 
9.1. DC analysis 
Let the supply voltages be ± 15 V and both inputs connected to ground. From fig. 63 and I_{11} = I_{REF} . which results in
Symmetrically I_{C1} = I_{C2} = I and as b_{N} >> 1 we have:


From fig. 64 we may conclude I_{9} @ I_{8} @ 2I and and finally I_{1} = I_{2} @ I_{3} = I_{4} = 9.5 mA.
Transistors T_{1} to T_{4}, T_{8} and T_{9} establish a negative feedback loop that stabilises
I to a value approximately equal to I_{10} / 2. In fact, if for some reason I increases, we’ll
successively have 

The currents in the mirror that loads the differential pair are I_{5} @ I_{6} @ I, as can be seen in fig. 65 and disregarding both I_{B16} and I_{B7}.
On the other hand: This shows that I_{B7} is indeed very small. 

Let’s now analyse the second stage (fig. 66).
Ignoring I_{B23}, I_{13B} @ 0.75 I_{REF} = 550 mA = I_{17} the result of which is
and Again, according to our approximations, we have I_{B16} << I. 

Finally, let’s see the currents in the output stage (fig. 67 where, because of their very small value, we ignored the resistors R_{6} e R_{7}). If I_{B14} and I_{B20} are approximately zero we will have I_{23} @ 0.25 I_{REF} = 180 mA, and therefore I_{B23} = 3.6 mA, which is really much smaller than I_{17} = 550 mA. From we get and
V_{BE18} = 588 mV, I_{18} = 165 mA, I_{R10} = 14.7 mA and 

Then and the potential between the base T_{14} and of T_{20} is V_{BB} = 0.588 + 0.529 = 1.117 V As we can see that I_{14} = I_{20} = 152 mA. 
9.2. Small signal analysis 
In the small signal analysis we will evaluate the differential voltage gain, the input differential resistance as well as the output resistance. To compute the gain we suppose that the OpAmp is loaded with R_{L} = 2 kW, since this is the usual situation for the gain specification in the data sheets. Fig. 68 shows the equivalent circuit for low frequency small signals where the active load effect of the current mirror, on the differential pair, is represented by a controlled source v_{d} / 4 r_{e}. 

Let’s also remark that the follower pair is represented by a CC configuration in which the transistor labelled T_{14,20} represents the corresponding set of transistors, which is a fairly accurate approximation. However, the follower pair has to cope with large signals and therefore its gain varies along the cycle. Moreover the fact that one of the transistors is an npn while the other is a pnp, is a reason for asymmetry. Let’s analyse how much the gain may vary:
If we have I_{C} = 5 mA, then r_{o14} = 25 kW, r_{o20} = 10 kW and r_{e} = 5 W, for both transistors, we get A_{14} = 0.997 and A_{20} = 0.997 Whilst for I_{C} = 150 mA, with r_{o14} = 833 kW, r_{o20} = 333 kW and r_{e} = 167 W, for both transistors, the result will be A_{14} = 0.923 and A_{20} = 0.923 As we can see, taking A_{14,20} @ 1 is still a good approximation. T_{23} is an emitter follower that responds only to small signals, but with a varying load. The load may vary as follows:
R_{i20} = 85 kW  T_{20} having a collector current I_{C} = 5 mA As R_{o13A} = r_{o13A} = 278 kW, r_{o23} = 278 kW and r_{e23} = 139 W, we’ll have
Therefore, Again A_{23} @ 1 is a good approximation.
The limiting situations are Let’s take the smallest value that somehow compensates for the unit gain approximation. For T_{17}, that is a CE with emitter resistance configuration,
where R_{o13B} = r_{o13B} = 90.9 kW and r_{e17} = 45 W. To compute the resistance R_{o17}, we need the resistance R_{o16} and, to compute this one, R_{o4} and R_{o6}. To compute R_{o4}, the base node of T_{3} and T_{4} is considered as a virtual ground. This is only possible once the differential gain is being considered.
So, taking into account that
g_{m4} = 380 mA/V,
r_{p4} = 132 kW
and
r_{o4} = 5.26 MW, 

The value of R_{o6} can again be evaluated in the same way. In fact, the base circuit resistance of T_{6}, i.e.
the resistance of the external circuit is only 19 W (compute this value as an exercise), which is very small when compared to r_{}p6 . So, since
g_{m6} = 380 mA/V,
r_{}p6 = 526 kW
and
r_{o6} = 13.2 MW, We can now compute R_{o16}, which is the output resistance of a CC, with a base resistance R_{o4} // R_{o6} and r_{}p16 = 309 kW:
Finally, to compute R_{o17}, taking into account that 

Therefore A_{17} = 493 V/V.
We also want to get the value of T_{16} is a CC montage, but as the collector current is very small, will display a high value for r_{e}. We should make sure that the value doesn’t depart very much from unity:
where r_{o16} = 7.72 MW and r_{e16} = 1.54 kW, therefore A_{16} = 0.923.
The input resistance is: Finally, for the differential pair we have:
where r_{e} = 2.63 kW (approximately common to T_{1} – T_{4}). It results that A_{1} = 474 V/V
and finally
To compute R_{id} is trivial. Reporting to fig. 68, we can see that On the other hand, computing R_{o}, i.e., the output resistance of the complementary symmetry follower pair, can only be obtained as an average value. In fact, as the complementary pair works with large signals the output resistance will depend upon which transistor is conducting as well as upon its current. If T_{20} is supplying the current
where
As r_{o18} is very small compared to r_{o13A} (278 kW), we will have The value of r_{e20} depends critically on the current.
For
I_{C} = 150 mA
r_{e} = 167 W Therefore, the value can vary between 66 and 228 W. The data sheets specify the value 75 W. 