Em Português

Miguel Lino Magalhães da Silva Department of Electrical and Computer Engineering Faculty of Engineering, University of Oporto Rua Dr. Roberto Frias, 4200-465 Porto, Portugal Office I223 Email: [email protected]

Brief CV

Phd student in  Electrical and Computers Engineering at Faculty of Engineering of Porto University.

MSc in Artificial Intelligence and Computing, by the Porto University in March 2004.

BSc degree in Electrical and Computers Engineering by the Faculty of Engineering of Porto University in August 2000.

Research

Research interests

Dynamically Reconfigurable FPGAs.

Reconfigurable systems management.

Programming reconfigurable systems.

Artificial Intelligence in reconfigurable systems.

Research Projects

Past

POCTI/33842/ESE/2000 "Concurrent Test Methods for Reconfigurable Hardware Systems (based on partial and dynamically reconfigurable FPGAs)".

PIDEEC/05-03 "Dynamic Management of Reconfigurable Resources: Operating System Kernel for FPGAs".

Present

Phd in Electrical and Computer Engineering entitled "Management of Dynamically Reconfigurable Resources for Hybrid CPU/FPGA Systems". (Abstract).

Publications

Theses

• Miguel L. Silva, Tools to Support the Concurrent Test of Partial Dynamically Reconfigurable FPGAs (Abstract) (PDF-Portuguese),MS Thesis, Faculty of Economy, University of Porto,March 2004.

Book contributions

• Manuel G. Gericota, Gustavo R. Alves, Miguel L. Silva, José M. Ferreira, " Run-time Defragmentation for Dynamically Reconfigurable Hardware", in: New Algorithms, Architectures and Applications for Reconfigurable Computing, editors: Patrick Lysaght & Wolfgang Rosenstiel. Springer, 2005. ISBN 1-4020-3127-0

Conference papers

• Miguel L. Silva, João Canas Ferreira, "Generation of hardware modules for run-time reconfigurable hybrid CPU/FPGA systems", XX Conference on Design of Circuits and Integrated Systems (DCIS'2005), Lisboa, Portugal, November 2005
• Miguel L. Silva, João Canas Ferreira, "Using a Tightly-Coupled Pipeline in Dynamically Reconfigurable Platform FPGAs", 8th Euromicro Conference on Digital System Design (DSD'2005), Porto, Portugal, September 2005
• Miguel M. Silva, João Canas Ferreira, "Run-time reconfiguration support for FPGAs with embedded CPUs: The hardware layer", 12th Reconfigurable Architectures Workshop (RAW 2005), Denver, Colorado, USA, April 2005
• Miguel M. Silva, João Canas Ferreira, "Development of Applications with Run-Time Support for Dynamic Reconfiguration", Jornadas sobre Sistemas Reconfiguráveis (REC 2005), Faro, Portugal, February 2005
• Miguel M. Silva, "Gestão de recursos reconfiguráveis dinamicamente em sistemas combinados CPU/FPGA", Jornadas sobre Sistemas Reconfiguráveis (REC 2005), Faro, Portugal, February 2005
• Manuel G. Gericota, Gustavo R. Alves, Miguel L. Silva, José M. Ferreira, "Run-Time Management of Logic Resources on Reconfigurable Systems", Proceedings of the Design, Automation and Test in Europe 2003 Conference and Exhibition (DATE'2003), Munich, Germamy, March 2003, pp. 974-979
• Manuel G. Gericota, Gustavo R. Alves, Miguel L. Silva, José M. Ferreira, "Programmable Logic Devices: A Test Approach for the Input/Output Blocks and Pad-to-Pin Interconnections", 4^th IEEE Latin-American Test Workshop (LATW'2003) Digest of Papers, Natal, Brazil, February 2002, pp. 72-77
• Manuel G. Gericota, Gustavo R. Alves, Miguel L. Silva, José M. Ferreira, "Concurrent replication of active logic blocks: A core solution for online testing and logic space defragmentation in reconfigurable systems", DAK-forum 2003, Trondheim, Norway, October 2003
• Manuel G. Gericota, Gustavo R. Alves, Miguel L. Silva, José M. Ferreira, "On-line Testing of FPGA Logic Blocks Using Active Replication", Proceedings of the Norsk Informatikkonferanse (NIK'2002), Kongsberg, Norway, November 2002, pp. 167-178
  
• Manuel G. Gericota, Gustavo R. Alves, Miguel L. Silva, José M. Ferreira, "On-line Defragmentation for Run-Time Partially Reconfigurable FPGAs", Proceedings of the 12^th International Conference on Field Programmable Logic and Applications : Reconfigurable Computing is Going Mainstream (FPL'2002), La Grande-Motte, Montpellier, France, September 2002, pp. 302-311, edited by Manfred Glesner, Peter Zipf, Michel Renovell. 1^st edition, Berlin : Springer, 2002. 1187 p. Lecture Notes in Computer Science 2438. ISBN 3-540-44108-5
• Manuel G. Gericota, Gustavo R. Alves, Miguel L. Silva, José M. Ferreira, "Active Replication: Towards a Truly SRAM-based FPGA On-Line Concurrent Testing", Proceedings of the 8^th IEEE On-Line Testing Workshop (IOLTW'2002), Île de Bendor, France, July 2002, pp. 165-169
• Manuel G. Gericota, Gustavo R. Alves, Miguel L. Silva, José M. Ferreira, "AR²T: Implementing a Truly SRAM-based FPGA On-Line Concurrent Testing", 7^th IEEE European Test Workshop (ETW'2002) Informal Digest, Corfu, Greece, Maiy 2002, pp. 61-66
• Manuel G. Gericota, Gustavo R. Alves, Miguel L. Silva, José M. Ferreira, "A Novel Methodology for the Concurrent Test of Partial and Dynamically Reconfigurable SRAM-based FPGAs", Proceedings of the Design, Automation and Test in Europe 2002 Conference and Exhibition (DATE'2002), Paris, France, March 2002, pp. 1126
• Manuel G. Gericota, Gustavo R. Alves, Miguel L. Silva, José M. Ferreira, "Dynamic Replication: The Core of a Truly Non-Intrusive SRAM-based FPGA Structural Concurrent Test Methodology", 3^nd IEEE Latin-American Test Workshop (LATW'2002) Digest of Papers, Montevideo, Uruguay, February 2002, pp. 70-75
• Manuel G. Gericota, Gustavo R. Alves, Miguel L. Silva, José M. Ferreira, "DRAFT: An On-line Concurrent Test for Partial and Dynamically Reconfigurable FPGAs", Proceedings of the 16^th Conference on Design of Circuits and Integrated Systems (DCIS'2001), Porto, Portugal, November 2001, pp. 553-558
• Manuel G. Gericota, Gustavo R. Alves, Miguel L. Silva, José M. Ferreira, "DRAFT: An On-Line Fault Detection Method for Dynamic and Partially Reconfigurable FPGAs", Proceedings of the 7^th IEEE On-Line Testing Workshop (IOLTW'2001), Giardini Naxos - Taormina, Italy, July 2001, pp. 34-36
• Manuel G. Gericota, Gustavo R. Alves, Miguel L. Silva, José M. Ferreira, "DRAFT: A Scanning Test Methodology for Dynamic and Partially Reconfigurable FPGAs", 6^th IEEE European Test Workshop (ETW'2001) Informal Digest, Saltsjöbaden, Stockolm, Sweden, May-June 2001, pp. 113-115
• Manuel G. Gericota, Gustavo R. Alves, Miguel L. Silva, José M. Ferreira, "Testando...", 2^as Jornadas Científicas do ISEP, Porto, Portugal, Maio de 2001
• M. da Silva,M. d. R. de Pinho, A. Sampaio and  V. Vieira  , "Sub-Optimal Control for Linear Quadratic Problems", Proceedings of the 4th Portuguese Meeting on Automatic Control, Controlo 2000, pp. 85-90, Outubro 2000, Guimarães, Portugal

Some Developed Software

WARNING this software is not supported (and has poor comments :)), the author is not responsible for any damages it may cause ,etc..., use at your own risk.

ppjtagvirtex.zip A XHWIF and a DLL, and source files, to configure a Xilinx Virtex XCV200 through JTAG Port using Xilinx parallel cable. Needs Port I/O Driver.

WARNING this software was developed with a Virtex XCV200 in mind, only works with this device, although it could work with others with some alterations.

VirtexPART A Java program, to configure a Xilinx Virtex with full and partial configurations, also enables viewing of states and route changing. Needs ppjtagvirtex and JBits 2.7