WRC'2016, Prague, January 19
| Time frame | Event |
|---|---|
| 08:45 - 10:00 | HiPEAC Keynote |
| 10:00 - 10:15 | Opening Session |
| 10:15 - 11:00 | Keynote 1 Chair: Steven Derrien, University of Rennes 1, France - Peter Hofstee, IBM, USA Accelerating Big Data Systems with Reconfigurable Acceleration |
| 11:00 - 11:30 | Coffee Break |
| 11:30 - 12:15 | European Project Session: SAVE Chair: Dirk Stroobandt, University of Ghent, Belgium - Marcello Pogliani, Gianluca C. Durelli, Ettore M. G. Trainiti, Tobias Becker, Peter Sanders, Cristiana Bolchini and Marco D. Santambrogio: Quality of Service Driven Runtime Resource Allocation in Reconfigurable HPC Architectures - Heinrich Riebler, Gavin Vaz, Christian Plessl, Ettore M.G. Trainiti, Gianluca C. Durelli, Cristiana Bolchini: Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems - D.Bakoyannis, O. Tomoutzoglou, G.Kornaros and M.Coppola: Efficient Dispatching to Co-processors over PCIe |
| 12:15 - 13:00 | Technical Session 1: Architectures for Signal Processing Chair: Dietmar Fey, University of Erlangen-Nürnberg, Germany - Yousef Baroud, Nguyên Lê, Zhe Wang, Steffen Kiess, Seyyed Mahdi Najmabadi and Sven Simon: A Parallel Codec Architecture for Marker-Free Variable Length Code Streams - Okan Palaz, H. Fatih Ugurdag, Özgür Özkurt, Bugra Kertmen and Faruk Dönmez: RImCom: Raster-order Image Compressor for embedded video applications - Mohamed El-Hadedy, Martin Margala and Kevin Skadron: Area-Speed-Efficient Transpose-Memory Architecture for Signal-Processing Systems |
| 13:00 - 14:00 | Lunch & Exhibition |
| 14:00 - 14:45 | Keynote 2 Chair: João Cardoso, University of Porto and INESC TEC, Portugal - Ronan Keryell, Xilinx Research Labs, Ireland From Modern FPGA To High-Level Post-Modern C++ Abstraction For Heterogeneous Computing With OpenCL SYCL & SPIR-V |
| 14:45 - 15:30 | Technical Session 2: Applications of FPGAs Chair: Dionisios Pnevmatikatos, Technical University of Crete (TUC), Greece - Emmanouil Kousanakis, Apostolos Dollas and Euripides Sotiriades: An Architecture for the Acceleration of the Hodgkin and Huxley Spiking Neural Network Model on the Convey HC-2ex FPGA-Based Processor - Thomas Preußer and Benedikt Reuter: Putting Queens in Carry Chains, No 27 - Konstantinos Maragos, Panagiotis Kontzilas, George Lentaris, Christos Spatharakis, Stefanos Dris, Paraskevas Bakopoulos, Hercules Avramopoulos and Dimitrios Soudris: A Real-Time, High-Performance FPGA Implementation of a Feed-Forward Equalizer for Optical Interconnects |
| 15:30 - 16:00 | Coffee Break |
| 16:00 - 16:30 | Technical Session 3: HLS & Benchmarking Chair: Pedro Diniz, ISI/USC, USA - Hamid Reza Zohouri, Naoya Maruyama, Aaron Smith, Motohiko Matsuda and Satoshi Matsuoka: Towards Understanding the Performance of FPGAs using OpenCL Benchmarks - Vasileios Tsoutsouras, Konstantina Koliogeorgi, Sotirios Xydis and Dimitrios Soudris: HLS code transformation strategies and directives exploration for FPGA accelerated ECG analysis |
| 16:30 - 17:30 |
Panel: Is the embedded revolution dead? Or is it just the microprocessor? What is
next? Will reconfigurable computing be the key? Moderator: Juergen Becker, KIT, Germany
H. Peter Hofstee (IBM) |
| 17:30 | Closing Session |