DTFT Special Session

Dependability, Testing and Fault Tolerance in Digital Systems


The Euromicro Conference on Digital System Design (DSD) addresses all aspects of (embedded) digital and mixed hardware/software system engineering. It is a discussion forum for researchers and engineers working on state-of-the-art investigations, developments and applications. It focuses on advanced system design automation concepts, paradigms, methods and tools, as well as modern implementation technologies enabling an effective and efficient development of high-quality systems for demanding applications.

Every designed system has to be tested several times during its life-time – during its design, production, and its in-field operation. The need for testing strictly depends on the actual use of the system, e.g., if the system can be repaired or not, and on the requirements for the system, e.g., if the system must be dependable, fault tolerant, etc. The design must reflect these requirements. The special session on “Dependability, Testing and Fault Tolerance in Digital Systems” (DTFT) addresses emerging issues, hot problems, new solution methods and their hardware and software implementations in all fields of digital and analog/mixed-signal system dependability and testing. It is especially focused on testing, dependability, and fault-tolerance of SoC based designs and modern embedded applications.

Papers on any of the following and related topics can be submitted to the special session:

  • Diagnosis & testing of embedded systems, SoC and NoC testing Memory and CPU testing
  • Analog, mixed-signal and RF, IDDQ and current testing
  • Built-In Self-Test: off-line BIST and on-line BIST, test compression methods
  • Testability analysis, synthesis for testability
  • Error detection and correction, on-line testing, design of checkers, fault injection techniques
  • Design of dependable (robust) circuits and systems, duplex designs, TMR based designs
  • Dependability modeling, dependability analysis and validation
  • Defect/fault tolerant architectures (SoCs, NoCs, embedded systems)
  • FPGA based fault tolerant systems, partial/full reconfiguration based methods
  • Formal approaches in fault tolerant systems design
  • System diagnosis
  • Dependable design in practical applications


Authors are encouraged to submit their manuscripts to www.easychair.org/conferences/?conf=dsd2015. Should an unexpected web access problem be encountered, please contact the Program Chair by email (dsd2015@easychair.org).

Each manuscript should include the complete paper text, all illustrations, and references. The manuscript should conform to the IEEE format: single-spaced, double column, US letter page size, 10-point size Times Roman font, up to 8 pages. In order to conduct a blind review, no indication of the authors’ names should appear in the manuscript, references included.

CPS, Conference Publishing Services, publishes the DSD Proceedings (submitted for ISI indexing), submitted to the IEEE Xplore Digital Library. Extended versions of selected best papers will be published in a special issue of the ISI indexed “Microprocessors and Microsystems: Embedded Hardware Design” Elsevier journal.


Deadline for paper submission: April 12th, 2015 (EXTENDED)
Notification of acceptance: June 15th, 2015
Camera ready papers: June 29th, 2015


Hana Kubátová (CTU in Prage, CZ)
Zdenek Kotásek (BUT, Brno, CZ)


S. Bernard, LIRMM, Montpellier (FR)
Ch. Bolchini, Politecnico di Milano (IT)
R. Dobai, BUT, Brno (CZ)
G. Fey, Univ. of Bremen (DE)
P. Fišer, CTU in Prague (CZ)
T. Garbolino, Silesian TU, Gliwice (PL)
S. Kajihara, Kyushu Ins. of Tech. (JP)
M. Keim, Mentor Graphics, Wilsonville (US)
Z. Kotásek, BUT, Brno (CZ)
A. Krasniewski, WUT, Warsaw (PL)
H. Kubátová, CTU in Prague (CZ)
I. Levin, Tel Aviv University (IL)
H. Manhaeve, Q-Star Test (BE)
A. Miele, Politecnico di Milano (IT)
G. Di Natale, LIRMM (FR)
A. Orailoglu, UC, San Diego (US)
S. Racek, U. of West Bohemia (CZ)
J. Raik, Tallin U. of Technology (EE)
G. Russell, U. of Newcastle u. Tyne (UK)
R. Růžička, BUT, Brno (CZ)
T. Sasao, Meiji University, Kawasaki (JP)
T. Sato, Fukuoka University (JP)
H. Shimada, Nagoya University (JP)
M. Sonza Reorda, Politecnico di Torino (IT)
A. Steininger, Vienna U. of Techn. (AT)
V. Stopjaková, STU, Bratislava (SK)
R. Ubar, TTU, Tallinn (EE)
H. T. Vierhaus, Brandenburg U. Tech. (DE)
Y. Zorian, Virage Logic, CA (US)


Hana Kubátová
Czech Technical University in Prague
Faculty of Information Technology
Department of Digital Design
Thákurova 9, 160 00 Prague 6, Czech Republic
Tel.: +420 224 359 840