FDR Special Session

Flexible Digital Radio


Over the past decade, flexible radio has been a very thought after topic, accompanying the boom of wireless technologies. Digital radios have to handle more and more different air interfaces which often exhibit complex algorithms to improve spectrum efficiency, and to push the performance closer to the channel capacity limit. Hence, modern transceivers have to cope with computationally demanding processing, while being flexible enough to run multiple standards. Harsh design constraints are thus to be considered: flexibility, efficiency, size, power consumption, cost, and real time processing. This special session addresses all aspects regarding both the digital architecture design and methodologies concepts for multi-standard, multi-mode flexible radios. Papers on any of the following and related topics will be considered for the special session:

  • FDR for multi-standard and cognitive radio (Algorithm / Architecture optimization)
  • Design modelling and HW / SW partitioning for flexible radios
  • High level design approach and design space exploration methodology for flexible radio
  • HW accelerators for flexible radios
  • HW factorization and parameterization techniques
  • Digital front end architectures and design (incl. digital correction of RF impairments)
  • Parallel processing for real-time digital communication systems
  • MPSoC and NoC based flexible radios
  • Power consumption aware radios
  • Abstraction layers and virtualization techniques for multi-standard radio
  • Open platforms for multi-standard support
  • Flexible radio prototypes, applications, and case studies


Authors are encouraged to submit their manuscripts to http://www.easychair.org/conferences/?conf=dsd2015. Should an unexpected web access problem be encountered, please contact the Program Chair by email (dsd2015@easychair.org).

Each manuscript should include the complete paper text, all illustrations, and references. The manuscript should conform to the IEEE format: single-spaced, double column, US letter page size, 10-point size Times Roman font, up to 8 pages. In order to conduct a blind review, no indication of the authors’ names should appear in the manuscript, references included.

CPS, Conference Publishing Services, publishes the DSD Proceedings (submitted for ISI indexing), submitted to the IEEE Xplore Digital Library. Extended versions of selected best papers will be published in a special issue of the ISI indexed “Microprocessors and Microsystems: Embedded Hardware Design” Elsevier journal.


Deadline for paper submission: April 12th, 2015 (EXTENDED)
Notification of acceptance: June 15th, 2015
Camera ready papers: June 29th, 2015


Dominique Noguet (CEA – Minatec, FR)


L. Fanucci (U. of Pisa, IT)
S. Filin (NICT, JP)
A. Gelonch (U. Polit. de Catalunya, SP)
A. Ghazel (Supcom, TN)
M. Ikekawa (NEC Corporation, JP)
G. Masera (Polit. Torino, IT)
C. Moy (Supélec, FR)
O. Muller (Grenoble INP, FR)
D. Noguet (CEA-LETI, FR)