Mixed Criticality System Design, Implementation and Analysis
Modern embedded appliances already integrate a multitude of functionalities with potentially different criticality levels into a single system and this trend is expected to grow in the near future. The integration of multiple functions with different criticality and certification assurance levels on a shared computing platform constitutes a mixed-criticality system (MCS). Mixed-criticality systems range from lowest assurance requirements up to the highest criticality levels (e.g., DAL A in RTCA DO-178B or SIL4 in EN ISO/IEC 61508). In many domains such as automotive, avionics and industrial control, the economic success depends on the ability to design, implement, qualify and certify advanced real-time embedded systems within bounded time, effort and costs. Without appropriate preconditions, the integration of mixed-criticality subsystems can lead to a significant and potentially unacceptable increase of engineering and certification costs. There are several ongoing research initiatives studying mixed-criticality integration in single and multicore processors, as well as on distributed systems. Key challenges are the combination of software virtualization and hardware segregation and the extension of partitioning mechanisms jointly addressing significant extra-functional requirements (e.g., time, energy and power budgets, adaptivity, reliability, safety, security, volume, weight, etc.) along with a proven development and certification methodology. To support the design and implementation of mixed-criticality systems, new design techniques and tools for the analysis of extra-functional properties are required.
TOPICS OF INTEREST INCLUDE (BUT ARE NOT LIMITED TO):
Requirements engineering and traceability for mixed-criticality systems, mechanisms for temporal and spatial partitioning, physical resource virtualization for temporal and spatial segregation, resource partitioning to achieve composability in multiple dimensions (time, power, temperature, …), resources partitioning techniques at chip and cluster level, solutions for communication resource partitioning, (incremental) verification of extra-functional properties, composable certification techniques, modular safety cases, multi-physical component- and model-based design techniques, (composable) analysis of extra-functional properties (like timing, power, temperature, safety and security), reliability and energy integrity of services with mixed-criticality, dependable operation of battery-driven/mobile mixed-criticality systems, dynamic resource management for services of mixed-criticality, design-space exploration for multi-physical mixed-criticality systems, industrial case-studies.
Authors are encouraged to submit their manuscripts to http://www.easychair.org/conferences/?conf=dsd2015. Should an unexpected web access problem be encountered, please contact the Program Chair by email (email@example.com).
Each manuscript should include the complete paper text, all illustrations, and references. The manuscript should conform to the IEEE format: single-spaced, double column, US letter page size, 10-point size Times Roman font, up to 8 pages. In order to conduct a blind review, no indication of the authors’ names should appear in the manuscript, references included.
CPS, Conference Publishing Services, publishes the DSD Proceedings (submitted for ISI indexing), submitted to the IEEE Xplore Digital Library. Extended versions of selected best papers will be published in a special issue of the ISI indexed “Microprocessors and Microsystems: Embedded Hardware Design” Elsevier journal.
Deadline for paper submission: April 12th, 2015 (EXTENDED)
Notification of acceptance: June 15th, 2015
Camera ready papers: June 29th, 2015
MCSDIA SESSION CHAIR
Kim Grüttner (OFFIS, DE)
Eugenio Villar (TEISA U Cantabria, ES)
MCSDIA PROGRAM COMMITTEE
Kim Grüttner (OFFIS, DE)
Eugenio Villar (U Cantabria, ES)
Sanjoy Baruah (U North Carolina, USA)
Gedare Bloom (George Washington U, USA)
Francisco J. Cazorla (BSC & IIIA-CSIC, ES)
Arvind Easwaran (Nanyang TU, Singapore)
William Fornaciari (Politecnico di Milano, IT)
Franco Fummi (U Verona, IT)
Kees Goossens (TU/e, NL)
Philipp A. Hartmann (OFFIS, DE)
Knut Hufeld (Infineon, DE)
Silvia Mazzini (INTECS, IT)
Julio Medina (U Cantabria, ES)
Moritz Neukirchner (Elektrobit, DE)
Roman Obermaisser (U Siegen, DE)
Ingo Sander (KTH, SE)
Ingo Stierand, (CvO University Oldenburg, DE)
Jean-Loup Terraillon (ESA, NL)
Salvador Trujillo (IK4-IKERLAN, ES)
Andreas von Schwerin (Siemens, DE)
Roberto Zafalon (STMicroelectronics, IT)
OFFIS – Institute for Information Technology
Hardware/Software Design Methodology
D-26121 Oldenburg – Germany
Phone/Fax.: +49 441 9722-228/278