Multicore Systems: Design and Applications
The microprocessor industry moved to multi-core and many-core systems as an efficient alternative to reduce power consumption while improving the performance. These systems are dominating the computing systems, ranging from high-performance computers, to servers and embedded systems. Moreover, the number of cores in these systems is expected to continue to increase dramatically during the next years.
Although these systems can potentially provide significant performance benefits, in practice, exploiting the multi/many-cores’ inherent shared resources still represents an important challenge for researchers and engineers. Innovations on, among others, portable programming models, load balancing in heterogeneous systems, 3D-stacked or wide-I/O-enabled memory hierarchies, and advanced compilation methods are required to utilize at best the increasingly-adaptive hardware, in the presence of highly-dynamic workload.
This special session will provide a forum for engineers and scientists to address challenges, and present new ideas in the multicore and many-core fields, as well as introduce emerging implementations, and tackle related issues with respect to improving system performance and reducing energy consumption for entire systems. Authors are invited to submit high quality papers representing original work in (but not limited to) the following topics targeting multicore, many-core, multithreaded processors:
- Performance and power consumption trade-off in emerging applications, e.g., object recognition, and tracking, on existing many-core platforms or FPGA prototypes.
- Run-time trade-offs in heterogeneous multi/many-core architectures: scheduling, allocation, workload balancing, for energy efficiency, resilience and performance.
- Portable and unified programming and execution models for heterogeneous multi/many-core architectures.
- Novel parallel realizations for highly demanding applications.
- Memory hierarchy: last level cache management, placement/replacement algorithms, NUCA, memory controllers and interfaces, coherence protocols.
- Addressing scalability for exascale computing.
Authors are encouraged to submit their manuscripts to http://www.easychair.org/conferences/?conf=dsd2015. Should an unexpected web access problem be encountered, please contact the Program Chair by email (email@example.com).
Each manuscript should include the complete paper text, all illustrations, and references. The manuscript should conform to the IEEE format: single-spaced, double column, US letter page size, 10-point size Times Roman font, up to 8 pages. In order to conduct a blind review, no indication of the authors’ names should appear in the manuscript, references included.
CPS, Conference Publishing Services, publishes the DSD Proceedings (submitted for ISI indexing), submitted to the IEEE Xplore Digital Library. Extended versions of selected best papers will be published in a special issue of the ISI indexed “Microprocessors and Microsystems: Embedded Hardware Design” Elsevier journal.
Deadline for paper submission: April 12th, 2015 (EXTENDED)
Notification of acceptance: June 15th, 2015
Camera ready papers: June 29th, 2015
MSDA SESSION CHAIR
Julio Sahuquillo (Universitat Politècnica de València, SP)
Anca Molnos (Université Grenoble Alpes, CEA-LETI, FR)
MSDA PROGRAM COMMITTEE
Sandro Bartolini, Univ. di Siena, IT
João Canas Ferreira, Univ. do Porto, PT
Sorin Cotofana, Delft UT, NL
Pierfrancesco Foglia, Univ. di Pisa, IT
María E. Gómez, UPV Valencia, SP
Kees Goossens, Eindhoven UT, NL
Roberto Giorgi, Univ. di Siena, IT
José A. Gregorio, U. Cantabria, SP
Houcine Hassan, UPV Valencia, SP
Ben Juurlink, TU Berlin, DE
David Kaeli, Northeastern University, USA
Sonia Lopez, Rochester Inst. of Tech., USA
Julien Mottin, UGA, CEA-LETI, FR
Orlando Moreira, ST-Ericsson, NL
Salvador Petit, UPV Valencia, SP
Ana Varbanescu, U. Amsterdam, NL
Bart Vermeulen, NXP Semiconductors, NL
Universitat Politècnica de València
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Univ. Grenoble Alpes, F-38000,
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