DAY 1: Wednesday, August 26th, 2015
DAY 2: Thursday, August 27th, 2015
DAY 3: Friday, August 28th, 2015
DAY 1: Wednesday, August 26th, 2015
Room Funchal
- 10:00 – 11:00: RECONFIG-1 – Reconfigurable Computing (1)
- 11:30 – 13:00: ADES – Analysis and Design of Embedded Systems
- 15:30 – 16:30: AIGP – Advanced Image and Graphics Processing
- 17:00 – 18:00: SYNVER – Circuit Synthesis and Verification
Room Luanda
- 10:00 – 11:00: ASAIT – Arch. and Systems for Automotive and Intelligent Transportation
- 11:30 – 13:00: EPDSD-1 – European Projects in Digital System Design (1)
- 15:30 – 16:30: FDR – Flexible Digital Radio
- 17:00 – 18:00: EPDSD-2 – European Projects in Digital System Design (2)
Room Paris
- 10:00 – 11:00: ASHWPA-1 – Adv. Systems in Healthcare, Wellness and Pers. Assistance (1)
- 11:30 – 13:00: DTFT-1 – Dependability, Testing and Fault Tolerance in Digital Systems (1)
- 15:30 – 16:30: ETCS – Emerging Technologies and Circuit Synthesis
- 17:00 – 18:00: SDSG-1 – System Design for the Smart Grid (1)
RECONFIG-1 – Reconfigurable Computing (1)
Room Funchal – August 26th – 10:00-11:00
Chair: Horácio Neto
| Start | End | Presentation / Authors |
|---|---|---|
| 10:00 | 10:30 | Towards Efficient Field Programmable Pattern Matching Array |
| Vlastimil Kosar and Jan Korenek | ||
| 10:30 | 11:00 | An FPGA Framework for Genetic Algorithms: Solving the Minimum Energy Broadcast Problem |
| Pedro Santos; Jose C. Alves and João Canas Ferreira |
ADES – Analysis and Design of Embedded Systems
Room Funchal – August 26th – 11:30-13:00
Chair: Dionísio Barros
| Start | End | Presentation / Authors |
|---|---|---|
| 11:30 | 12:00 | Worst-case Throughput Analysis of SDF-based Parametrized Dataflow |
| Mladen Skelin; Marc Geilen; Francky Catthoor and Sverre Hendseth | ||
| 12:00 | 12:20 | A Scenario-Aware Dataflow Programming Model |
| Reinier van Kampenhout; Sander Stuijk and Kees Goossens | ||
| 12:20 | 12:40 | Integrating task migration capability in software tool-chain for data-flow applications mapped on multi-tiled architectures |
| Ashraf Elantably; Nicolas Fournel and Frédéric Rousseau | ||
| 12:40 | 13:00 | Hardware Support for Cost-Effective System-level Protection in Multi-Core SoCs |
| Georgios Kornaros; Ioannis Christoforakis; Othon Tomoutzoglou; Dimitrios Bakoyiannis; Kallia Vazakopoulou; Miltos Grammatikakis and Antonios Papagrigoriou |
AIGP – Advanced Image and Graphics Processing
Room Funchal – August 26th – 15:30-16:30
Chair: Leonel Nóbrega
| Start | End | Presentation / Authors |
|---|---|---|
| 15:30 | 15:50 | High Level Synthesis Design Flow for HEVC Intra Encoder on SoC-FPGA |
| Panu Sjövall; Janne Virtanen; Jarno Vanne and Timo D. Hämäläinen | ||
| 15:50 | 16:10 | Accelerating Clifford Algebra Operations using GPUs and an OpenCL code generator |
| Silvia Franchini; Antonio Gentile; Giorgio Vassallo and Salvatore Vitabile | ||
| 16:10 | 16:30 | Using Dynamic Reconfiguration to Reduce the Area of a JPEG Decoder on FPGA |
| Tiago Rodrigues and Mário Véstias |
SYNVER – Circuit Synthesis and Verification
Room Funchal – August 26th – 17:00-18:00
Chair: TomChen
| Start | End | Presentation / Authors |
|---|---|---|
| 17:00 | 17:20 | Bi-Decomposition using Boolean Relations |
| Anna Bernasconi; Robert K. Brayton; Valentina Ciriani; Gabriella Trucco and Tiziano Villa | ||
| 17:20 | 17:40 | A Bundled-Data Asynchronous Circuit Synthesis Flow Using a Commercial EDA Framework |
| Matheus Gibiluka; Matheus Moreira and Ney L. V. Calazans | ||
| 17:40 | 18:00 | Automation and Optimization of Coverage-driven Verification |
| Marcela Šimková and Zdeněk Kotásek |
ASAIT – Architectures and Systems for Automotive and Intelligent Transportation
Room Luanda – August 26th – 10:00-11:00
Chair: Smail Niar
| Start | End | Presentation / Authors |
|---|---|---|
| 10:00 | 10:30 | Investigation on AUTOSAR-compliant solutions for many-core architectures |
| Matthias Becker; Dakshina Dasari; Vincent Nélis; Moris Behnam; Luís Miguel Pinho and Thomas Nolte | ||
| 10:30 | 11:00 | Distributed parallel computing with low cost microcontrollers for high performance electric vehicles |
| Victor Azevedo and J. Dionísio Barros |
EPDSD-1 – European Projects in Digital System Design (1)
Room Luanda – August 26th – 11:30-13:00
Chair: Lech Jozwiak
| Start | End | Presentation / Authors |
|---|---|---|
| 11:30 | 12:00 | Harnessing Performance Variability: A HPC-oriented Application Scenario |
| Giuseppe Massari; Simone Libutti; Antoni Portero; Radim Vavrik; Stepan Kuchar; Vit Vondrak; Luca Borghese and William Fornaciari | ||
| 12:00 | 12:30 | The AXIOM Software Layers |
| Carlos Alvarez; Eduard Ayguade; Javier Bueno; Antonio Filgueras; Daniel Jimenez-Gonzalez; Xavier Martorell; Nacho Navarro; Dimitris Theodoropoulos; Dionisios Pnevmatikatos; Davide Catani; Claudio Scordino; Paolo Gai; Carlos Segura; Carles Fernandez; David Oro; Javier Rodriguez-Saeta; Pierluigi Passera; Alberto Pomella; Antonio Rizzo and Roberto Giorgi | ||
| 12:30 | 13:00 | EMC2 a Platform Project on Embedded Microcontrollers in Applications of Mobility Industry and the Internet of Things |
| Werner Weber; Alfred Hoess; Frank Oppenheimer; Bernd Koppenhöfer; Bastijn Vissers and Bjorn Nordmoen |
FDR – Flexible Digital Radio
Room Luanda – August 26th – 15:30-16:30
Chair: Dominique Noguet
| Start | End | Presentation / Authors |
|---|---|---|
| 15:30 | 15:50 | A Flexible Research Testbed for C-RAN |
| Diogo Riscado; Jorge Santos; Daniel Dinis; Gustavo Anjos; Daniel Belo; Nuno B. Carvalho and Arnaldo Oliveira | ||
| 15:50 | 16:10 | Reconfigurable Traffic-Aware Radio Interconnect for a 2048-core Chip Multiprocessor |
| Eren Unlu and Christophe Moy | ||
| 16:10 | 16:30 | An Agile and Wideband All-Digital SDR Receiver for 5G Wireless Communications |
| André Prata; Arnaldo Oliveira and Nuno B. Carvalho |
EPDSD-2 – European Projects in Digital System Design (2)
Room Luanda – August 26th – 17:00-18:00
Chair: Francesco Leporati
| Start | End | Presentation / Authors |
|---|---|---|
| 17:00 | 17:30 | Enhanced Quality Using Intensive Test Analysis on Simulators |
| Reda Nouacer; Manel Djemal; Smail Niar; Gilles Mouchard; Nicolas Rapin; Jean-Pierre Gallois; Philippe Fiani; François Chasterette; Toni Adriano and Bryan Mac-Eachen | ||
| 17:30 | 18:00 | Playful Supervised Smart Spaces (P3S): A framework for designing implementing and deploying multisensory play experiences for children with special needs |
| Giovanni Agosta; Luca Borghese; Carlo Brandolese; Francesco Clasadonte; William Fornaciari; Franca Garzotto; Mirko Gelsomini; Matteo Grotto; Cristina Fra'; Danny Noferi and Massimo Valla |
ASHWPA-1 – Advanced Systems in Healthcare, Wellness and Personal Assistance (1)
Room Paris – August 26th – 10:00-11:00
Chair: Francesco Leporati
| Start | End | Presentation / Authors |
|---|---|---|
| 10:00 | 10:30 | Implantable MEMS Pressure Sensors Modelling Tool |
| Jose Ángel Miguel; David Rivas; Yolanda Lechuga; Miguel Angel Allende and Mar Martinez | ||
| 10:30 | 11:00 | Estimation of Blood Pressure and Pulse Transit Time Using Your Smartphone |
| Alair Dias Junior; Srinivasan Murali; Francisco Rincon and David Atienza |
DTFT-1 – Dependability, Testing and Fault Tolerance in Digital Systems (1)
Room Paris – August 26th – 11:30-13:00
Chair: Hana Kubatova, Petr Fiser
| Start | End | Presentation / Authors |
|---|---|---|
| 11:30 | 12:00 | Reliable and Continuous Measurement of SET Pulse Widths |
| Varadan Savulimedu Veeravalli and Andreas Steininger | ||
| 12:00 | 12:20 | Measuring the Distribution of Metastable Upsets over Time |
| Thomas Polzer and Andreas Steininger | ||
| 12:20 | 12:40 | Generic Self Repair Architecture with Multiple Fault Handling Capability |
| Marcel Balaz and Stefan Kristofik | ||
| 12:40 | 13:00 | A System for Radiation Testing and Physical Fault Injection into the FPGAs and Other Electronics |
| Tomas Vanat; Jan Pospisil; Filip Krizek; Jozef Ferencei and Hana Kubatova |
ETCS – Emerging Technologies and Circuit Synthesis
Room Paris – August 26th – 15:30-16:00
Chair: Emad Samuel Malki Ebeid
| Start | End | Presentation / Authors |
|---|---|---|
| 15:30 | 16:00 | Biconditional-BDD Ordering for Autosymmetric Functions |
| Anna Bernasconi; Valentina Ciriani and Gabriella Trucco | ||
| 16:00 | 16:30 | Enhanced Spin-diode Synthesis Using Logic Sharing |
| Mayler Martins; Felipe Marranghello; Joseph Friedman; Alan Sahakian; Renato Ribas and Andre Reis |
SDSG-1 – System Design for the Smart Grid (1)
Room Paris – August 26th – 17:00-18:00
Chair: Rune Hylsberg Jacobsen
| Start | End | Presentation / Authors |
|---|---|---|
| 17:00 | 17:20 | A Glimpse of SmartHG Project Test-bed and Communication Infrastructure |
| Vadim Alimguzhin; Federico Mari; Igor Melatti; Enrico Tronci; Emad S. M. Ebeid; Søren A. Mikkelsen; Rune H. Jacobsen; Jorn K. Gruber; Barry Hayes; Francisco Huerta and Milan Prodanovic | ||
| 17:20 | 17:40 | Towards the use of Pairing-Based Cryptography for Resource-Constrained Home Area Networks |
| Rune H. Jacobsen; Søren Aagaard Mikkelsen and Niels Holm Rasmussen | ||
| 17:40 | 18:00 | Distributed Grid Storage by Ordinary House Heating Variations: a Swiss Case Study |
| Gilbert Maitre; Gillian Basso; Claudio Steiner; Dominique Gabioud and Pierre Roduit |
Poster Session (Wednesday)
Chair: Hélio Mendonça
| Title | Authors |
|---|---|
| Buffer Allocation for Dynamic Real-time Streaming Applications Running on a Multi-processor without Back-pressure | Hrishikesh Salunkhe; Alok Lele; Kees van Berkel and Orlando Moreira |
| A Framework for Dynamic Real-Time Reconfiguration | João Gabriel Reis; Antônio Augusto Fröhlich and Lucas Wanner |
| Minimization Method of Finite State Machines for Low Power Design | Adam Klimowicz; Valery Solov'Ev and Tomasz Grzes |
| Parameterizable Ethernet Network-on-Chip Architecture on FPGA | Helio F. Da Cunha Junior; Bruno Silva and Vanderlei Bonato |
| Dynamic Detection and Mitigation of DMA Races in MPSoCs | Selma Saidi and Yliès Falcone |
| Green Computing: Power Optimisation of VFI-based Real-time Multiprocessor Dataflow Applications | Waheed Ahmad; Philip Hölzenspies; Marielle I A Stoelinga and Jaco van de Pol |
| Low-cost Fault Localization and Error Correction for a Signed Digit Adder Design Utilizing the Self-dual Concept | Hossein Moradian Sardroudi and Jeong-A Lee |
| Novel C-Element Based Error Detection and Correction Method Combining Time and Area Redundancy | Jan Bělohoubek; Petr Fišer and Jan Schmidt |
| Software Fault Tolerance: the Evaluation by Functional Verification | Ondrej Cekan; Jakub Podivínský and Zdenek Kotasek |
| A Framework for Comprehensive Automated Evaluation of Concurrent Online Checkers | Pietro Saltarelli; Behrad Niazmand; Jaan Raik; Ranganathan Hariharan; Gert Jervan and Thomas Hollstein |
| Safe Drive Map Concept for Road Curve Monitoring | Pietro Dell'Acqua; Francesco Bellotti; Riccardo Berta; Alessandro De Gloria; Gautam Dange; Pratheep Paranthaman; Kay Massow and Fabian Maximilian Thiele |
| Information and communication technology research opportunities in dynamic charging for electric vehicle | Oussama Smiai; Francesco Bellotti; Alessandro De Gloria; Riccardo Berta; Angelos Amditis; Yannis Damousis and Andrew Winder |
| Consumer-centric and Service-oriented Architecture for the Envisioned Energy Internet | Søren Aagaard Mikkelsen and Rune Hylsberg Jacobsen |
DAY 2: Thursday, August 27th, 2015
Room Funchal
- 10:00 – 11:00: POWER – Power Design
- 11:30 – 13:00: RECONF-2 – Reconfigurable Computing (2)
- 15:30 – 17:00: TSTVER – Test and Verification
Room Paris
- 10:00 – 11:00: ASHWPA-2 – Adv. Systems in Healthcare, Wellness and Pers. Assistance (2)
- 11:30 – 13:00: AHSA-1 – Architectures and Hardware for Security Applications (1)
- 15:30 – 16:30: DTFT-2 – Dependability, Testing and Fault Tolerance in Digital Systems (2)
Room Luanda
- 10:00 – 11:00: MCSDIA-1 – Mixed Criticality System Design, Implem. and Analysis (1)
- 11:30 – 13:00: SDSG-2 – System Design for the Smart Grid (2)
- 15:30 – 16:30: DHCPS – Design of Heterogeneous Cyber-Physical Systems
POWER – Power Design
Room Funchal – August 27th – 10:00-11:00
Chair: José Machado da Silva
| Start | End | Presentation / Authors |
|---|---|---|
| 10:00 | 10:30 | Experimental Evaluation and Modeling of Thermal Phenomena on Mobile Devices |
| Matteo Ferroni; Alessandro Antonio Nacci; Matteo Turri; Marco Domenico Santambrogio and Donatella Sciuto | ||
| 10:30 | 11:00 | Exploiting Heterogeneity in Cache Hierarchy in Dark- Silicon 3D Chip Multi-Processors |
| Arghavan Asad; Ozcan Ozturk; Mahmood Fathy and Mohammad Reza Jahed-Motlagh |
RECONF-2 – Reconfigurable Computing (2)
Room Funchal – August 27th – 11:30-13:00
Chair: José Carlos Alves
| Start | End | Presentation / Authors |
|---|---|---|
| 11:30 | 12:00 | Automated Design of High Performance Integer Arithmetic Cores on FPGA |
| Ayan Palchaudhuri; Rajat Subhra Chakraborty and Durga Prasad Sahoo | ||
| 12:00 | 12:20 | Sparse Matrix Multiplication on a Reconfigurable Many-Core Architecture |
| João Pinhão; Wilson José; Horácio Neto and Mário Véstias | ||
| 12:20 | 12:40 | Computing Framework for Dynamic Integration of Reconfigurable Resources in a Cloud |
| Oliver Knodel and Rainer G. Spallek | ||
| 12:40 | 13:00 | Analysis and Comparison of Attainable Hardware Acceleration in All Programmable Systems-on-Chip |
| Valery Sklyarov; Iouliia Skliarova; João Silva and Alexander Sudnitson | ||
TSTVER – Test and Verification
Room Funchal – August 27th – 15:30-17:00
Chair: Raimund Ubar
| Start | End | Presentation / Authors |
|---|---|---|
| 15:30 | 16:00 | Unit-Based Functional IDDT Testing for Aging Degradation Monitoring in a VLIW Processor |
| Yong Zhao and Hans Kerkhof | ||
| 16:00 | 16:20 | Leveraging the Analysis for Invariant Independence in Formal System Models |
| Nils Przigoda; Robert Wille and Rolf Drechsler | ||
| 16:20 | 16:40 | Collision Based Attacks in Practice |
| Diop Ibrahima; Pierre-Yvan Liardet; Philippe Maurinne and Yanis Linge | ||
| 16:40 | 17:00 | Verification-driven Design Across Abstraction Levels – A Case Study |
| Nils Przigoda; Jannis Stoppe; Julia Seiter; Robert Wille and Rolf Drechsler |
ASHWPA-2 – Advanced Systems in Healthcare, Wellness and Personal Assistance (2)
Room Paris – August 27th – 10:00-11:00
Chair: Lech Jozwiak
| Start | End | Presentation / Authors |
|---|---|---|
| 10:00 | 10:20 | A Low Power 64-point Bit-Serial FFT Engine for Implantable Biomedical Applications |
| Lang Yang and Tom Chen | ||
| 10:20 | 10:40 | A smart mobile Lab-on-Chip-based medical diagnostics system architecture designed for evolvability |
| François Patou; Maria Dimaki; Winnie E. Svendsen; Claus Kjærgaard and Jan Madsen | ||
| 10:40 | 11:00 | Wireless Sensor Tag and Network for Improved Clinical Triage |
| João Borges dos Santos; Gabriel Blard; Arnaldo S. R. Oliveira and Nuno B.Carvalho |
AHSA-1 – Architectures and Hardware for Security Applications (1)
Room Paris – August 27th – 11:30-13:00
Chair: Paris Kitsos and Francesco Leporati
| Start | End | Presentation / Authors |
|---|---|---|
| 11:30 | 12:00 | Towards Zero Bit-Error-Rate Physical Unclonable Function: Mismatch-Based vs. Physical-Based Approaches in Standard CMOS Technology |
| Duhyun Jeon; Jong-Hak Baek; Dong Kyue Kim and Byong-Deok Choi | ||
| 12:00 | 12:20 | Integrated Sensor: A Backdoor for Hardware Trojan Insertions? |
| Xuan Thuy Ngo; Zakaria Najm; Shivam Bhasin; Debapriya Basu Roy; Jean-Luc Danger and Sylvain Guilley | ||
| 12:20 | 12:40 | Side-Channel Leakage Models for RISC Instruction Set Architectures from Empirical Data |
| Hermann Seuschek and Stefan Rass | ||
| 12:40 | 13:00 | Affine Coordinate Binary Edwards Curve Scalar Multiplier with Side Channel Attack Resistance |
| Apostolos Fournaris and Odysseas Koufopavlou |
DTFT-2 – Dependability, Testing and Fault Tolerance in Digital Systems (2)
Room Paris – August 27th – 15:30-16:30
Chair: Andreas Steininger
| Start | End | Presentation / Authors |
|---|---|---|
| 15:30 | 16:00 | On-line Device Replacement Techniques for SSD RAID |
| Alistair McEwan and Muhammed Ziya Komsul | ||
| 16:00 | 16:30 | Gate Resizing for Soft Error Rate Reduction in Nano-scale Digital Circuits Considering Process Variations |
| Mohsen Raji; Behnam Ghavami and Hossein Pedram |
MCSDIA-1 – Mixed Criticality System Design, Implementation and Analysis (1)
Room Luanda – August 27th – 10:00-11:00
Chair: Kim Grüttner
| Start | End | Presentation / Authors |
|---|---|---|
| 10:00 | 10:30 | Mixed-Criticality Embedded Systems – A Balance Ensuring Partitioning and Performance |
| Michael Paulitsch; Oscar Medina Duarte; Hassen Karray; Kevin Mueller; Daniel Muench and Jan Nowotsch | ||
| 10:30 | 11:00 | Enabling TDMA Arbitration in the Context of MBPTA |
| Milos Panic; Jaume Abella; Carles Hernandez; Eduardo Quiñones; Theo Ungerer and Francisco J Cazorla |
SDSG-2 – System Design for the Smart Grid (2)
Room Luanda – August 27th – 11:30-13:00
Chair: Emad Samuel Malki Ebeid
| Start | End | Presentation / Authors |
|---|---|---|
| 11:30 | 12:00 | SEMIAH: An Aggregator Framework for European Demand Response Programs |
| Rune Hylsberg Jacobsen; Dominique Gabioud; Gillian Basso; Pierre-Jean Alet; Armin Ghasem Azar and Emad Samuel Malki Ebeid | ||
| 12:00 | 12:20 | User Flexibility Aware Price Policy Synthesis for Smart Grids |
| Toni Mancini; Federico Mari; Igor Melatti; Ivano Salvo; Enrico Tronci; Jorn Gruber; Barry Hayes; Milan Prodanovic and Lars Elmegaard | ||
| 12:20 | 12:40 | An Extensible Simulator for Dynamic Control of Residential Area: Case Study on Heating Control |
| Gillian Basso; Pierre Ferrez; Dominique Gabioud and Pierre Roduit | ||
| 12:40 | 13:00 | Efficient Clustering of DERs in a Virtual Association for Profit Optimization |
| Vasileios Botsis; Nikolaos Doulamis; Anastasios Doulamis; Prodromos Makris and Emmanouel Varvarigos |
DHCPS – Design of Heterogeneous Cyber-Physical Systems
Room Luanda – August 27th – 15:30-16:30
Chair: Marc Geilen
| Start | End | Presentation / Authors |
|---|---|---|
| 15:30 | 15:50 | Composable Platform-Aware Embedded Control Systems on a Multi-Core Architecture |
| Juan Valencia; Dip Goswami and Kees Goossens | ||
| 15:50 | 16:10 | Low-cost Software Control-Flow Error Recovery |
| Ghazaleh Nazarian; Razvan Nane and Georgi Gaydadjiev | ||
| 16:10 | 16:30 | Network-aware virtual platform for the verification of embedded software for communications |
| C. Barnes; J.M. Cottin; D. Quaglia; E. Fraccaroli; A. Pegatoquet; F. Verdier; S. Angeleri |
Poster Session (Thursday)
Chair: Hélio Mendonça
| Title | Authors |
|---|---|
| Dataflow Support in x86_64 Multicore Architectures through Small Hardware Extensions | Andrea Mondelli; Nam Ho; Alberto Scionti; Marco Solinas; Antoni Portero and Roberto Giorgi |
| QEMU-Based Fault Injection for a System-Level Analysis of Software Countermeasures Against Fault Attacks | Andrea Höller; Armin Krieg; Tobias Rauter; Johannes Iber and Christian Kreiner |
| White-Box Error Effect Simulation for Assisted Safety Analysis | Sebastian Reiter; Alexander Viehl; Oliver Bringmann and Wolfgang Rosenstiel |
| A Many-Core Co-Processor for Embedded Parallel Computing on FPGA | Wilson José; Horácio Neto and Mário Véstias |
| Parallel native-simulation for multi-processing embedded systems | Alejandro Nicolas and Pablo Sanchez |
| A Comparison of TERO and RO Timing Sensitivity for Hardware Trojan Detection Applications | Paris Kitsos and Artemios G. Voyiatzis |
| Clockwise Randomization of the Observable Behaviour of Crypto ASICs to Counter Side Channel Attacks | Zoya Dyka; Christian Wittke and Peter Langendoerfer |
| CLEFIA implementation with full key expansion | João Bittencourt; João Resende; Wagner Oliveira and Ricardo Chaves |
| Towards Ideal Arbiter PUF Design on Xilinx FPGA: a Practitioner's Perspective | Durga Prasad Sahoo; Rajat Subhra Chakraborty and Debdeep Mukhopadhyay |
| Linking the physical with the perceptual: Health and exposure monitoring with cyber-physical questionnaires | Christopher Scaffidi; Laurel Kincl; Diana Rohlman and Kim Anderson |
| Design for Dependability and Autonomy of a Wearable Cardiac and Coronary Monitor | José Machado da Silva; Cristina Oliveira; Bruno Mendes; Rúben Dias and Tiago Marques |
| A Modular Safety Case for an IEC-61508 Compliant Generic Hypervisor | Asier Larrucea Ortube; Juan Martin Perez; Irune Agirre Troncoso; Vicent Brocal and Roman Obermaisser |
DAY 3: Friday, August 28th, 2015
Room Funchal
- 10:00 – 11:00: ACCEL – Application-Specific Accelerators
- 11:30 – 13:00: SOCNOC – Systems and Networks on Chip
- 14:00 – 16:00: WiP – Work in Progress
Room Paris
- 10:00 – 11:00: MCSDIA-2 – Mixed Criticality System Design, Implem. and Analysis (2)
- 11:30 – 13:00: AHSA-2 – Architectures and Hardware for Security Applications (2)
Room Luanda
- 10:00 – 11:00: MSDA – Multicore systems: Design and Appplications
- 11:30 – 13:00: DTFT-3 – Dependability, Testing and Fault Tolerance in Digital Systems (3)
Room Londres
- 10:00 – 11:00: EPDSD-3 – European Projects in Digital System Design
ACCEL – Application-Specific Accelerators
Room Funchal – August 28th – 10:00-11:00
Chair: João Canas Ferreira
| Start | End | Presentation / Authors |
|---|---|---|
| 10:00 | 10:20 | An Embedded FTL for SSD RAID |
| Alistair McEwan and Irfan Mir | ||
| 10:20 | 10:40 | Scalable FPGA Accelerator of the NRM Algorithm for Efficient Stochastic Simulation of Large-Scale Biochemical Reaction Networks |
| Evangelos Koutsouradis; George Provelengios; Elias Kouskoumvekakis and Elias Manolakos | ||
| 10:40 | 11:00 | A Locality Aware Convolutional Neural Networks Accelerator |
| Runbin Shi; Zheng Xu; Zhihao Sun; Maurice Peemen; Ang Li; Henk Corporaal and Di Wu |
SOCNOC – Systems and Networks on Chip
Room Funchal – August 28th – 11:30-13:00
Chair: Arnaldo Oliveira
| Start | End | Presentation / Authors |
|---|---|---|
| 11:30 | 12:00 | Hardware Design Space Exploration with a New Dimension–IP Protection Robustness |
| Qiang Liu and Haie Li | ||
| 12:00 | 12:20 | TEST: Assessing NoC Policies Facing Aging and Leakage Power |
| Davide Zoni; Luca Borghese; Giuseppe Massari; Simone Libutti and William Fornaciari | ||
| 12:20 | 12:40 | SOC Power Management Strategy Based on Global Hardware Functional State Analysis |
| Hend Affes and Michel Auguin | ||
| 12:40 | 13:00 | An Analytic Approach on End-to-end Packet Error Rate Estimation for Network-on-Chip |
| Michael Vonbun; Stefan Wallentowitz; Andreas Oeldemann and Andreas Herkersdorf |
MCSDIA-2 – Mixed Criticality System Design, Implementation and Analysis (2)
Room Paris – August 28th – 10:00-11:00
Chair: Eugenio Villar
| Start | End | Presentation / Authors |
|---|---|---|
| 10:00 | 10:20 | IEC-61508 SIL 3-compliant Pseudo-Random Number Generators for Probabilistic Timing Analysis |
| Irune Agirre; Mikel Azkarate-askasua; Jon Perez; Carles Hernandez; Jaume Abella; Tullio Vardanega and Francisco J Cazorla | ||
| 10:20 | 10:40 | CAP: Communication-aware Allocation Algorithm for Real-Time Parallel Applications on Many-cores |
| Milos Panic; Eduardo Quiñones; Carles Hernandez; Jaume Abella and Francisco J Cazorla | ||
| 10:40 | 11:00 | Time-Triggered Extension Layer for On-Chip Network Interfaces in Mixed-Criticality Systems |
| Hamidreza Ahmadian and Roman Obermaisser |
AHSA-2 – Architectures and Hardware for Security Applications (2)
Room Paris – August 28th – 11:30-13:00
Chair: Francesco Leporati
| Start | End | Presentation / Authors |
|---|---|---|
| 11:30 | 12:00 | Suit up! Made-to-Measure Hardware Implementations of Ascon |
| Hannes Gross; Erich Wenger; Christoph Dobraunig and Christoph Ehrenhöfer | ||
| 12:00 | 12:20 | Fast and Secure Finite Field Multipliers |
| Danuta Pamula and Arnaud Tisserand | ||
| 12:20 | 12:40 | A petite and power saving design for the AES S-Box |
| Markus Stefan Wamser; Lukas Holzbaur and Georg Sigl | ||
| 12:40 | 13:00 | New ASIC/FPGA Cost Estimates for SHA-1 Collisions |
| Muhammad Hassan; Ayesha Khalid; Anupam Chattopadhyay; Christian Rechberger; Tim Gueneysu and Christof Paar |
MSDA – Multicore systems: Design and Appplications
Room Luanda – August 28th – 10:00-11:00
Chair: José Carlos Alves
| Start | End | Presentation / Authors |
|---|---|---|
| 10:00 | 10:30 | Systematic Reverse Engineering of Cache Slice Selection in Intel Processors |
| Gorka Irazoqui; Thomas Eisenbarth and Berk Sunar | ||
| 10:30 | 11:00 | A System-Level Simulation Framework for Evaluating of Resource Management Policies for Heterogeneous System Architectures |
| Antonio Miele; Gianluca Durelli; Marco Domenico Santambrogio and Cristiana Bolchini |
DTFT-3 – Dependability, Testing and Fault Tolerance in Digital Systems (3)
Room Luanda – August 28th – 11:30-13:00
Chair: Marcel Balaz
| Start | End | Presentation / Authors |
|---|---|---|
| 11:30 | 12:00 | Double Phase Fault Collapsing with Linear Complexity in Digital Circuits |
| Raimund Ubar; Lembit Jürimägi; Elmet Orasson; Galina Josifovska and Stephen Adeboye Oyeniran | ||
| 12:00 | 12:20 | Matching Detection and Correction Schemes for Soft Error Handling in Sequential Logic |
| Erol Koser; Felix Miller and Walter Stechele | ||
| 12:20 | 12:40 | A Detailed Characterization of Errors in Logic Circuits due to Single-event Transients |
| Nanditha P Rao and Madhav P Desai | ||
| 12:40 | 13:00 | Enhanced Metastability Characterization based on AC Analysis |
| Thomas Polzer and Andreas Steininger |
EPDSD-3 – European Projects in Digital System Design
Room Londres – August 28th – 10:00-11:00
Chair: Lech Jozwiak
| Start | End | Presentation / Authors |
|---|---|---|
| 10:00 | 10:20 | DEWI – Wirelessly into the Future |
| Werner Rom; Ramiro Robles; Peter Priller; Luis Dominguez; Javier Rivilla; Jani Koivusaari; Marjaana Komi and Willem van Driel | ||
| 10:20 | 10:40 | The Human Brain Project: High Performance Computing for Brain Cells Hw/Sw Simulation and Understanding |
| Egidio D'Angelo; Giovanni Danese; Giordana Florimbi; Francesco Leporati; Alessandra Majani; Stefano Masoli; Sergio Solinas and Emanuele Torti | ||
| 10:40 | 11:00 | Methodologies for the WCET Analysis of Parallel Applications on Many-core Architectures |
| Vincent Nelis; Patrick Meumeu Yomsi and Luis Miguel Pinho |
Work in Progress
Room Funchal – August 28th – 14:00-16:00
Chair: Erwin Grosspietsch
| Authors | Title |
|---|---|
| Stefan Scharoba; Heinrich Theodor Vierhaus | Towards an Interactive Dependability-Aware Design Space Exploration |
| Janusz Sosnowski; Marcin Iwínski | Experience with Monitoring Embedded Systems |
| Ivon Hálacek; Petr Fiser; Jan Schmidt | On Identification of XOR Gates in AIGs |
| Mónica Villaverde; David Pérez; Félix Moreno | Adaptive-Reactive Cooperative System for Object Identification |
| David Pérez; Mónica Villaverde; Félix Moreno | Towards an Adaptive Hardware Parallel Particle Filter |
| Alessandro Fontanella; Gino Mario Bertolotti; Giovanni Danese; Francesco Leporati | Visible Light Communication Transceiver with On-Off Keying Modulation for on Board Automotive Dataloggers |
| Benjamín Vega; Pedro P. Carballo; Pédro Hérnandez-Férnandez; Adrián Domínguez; Antonio Nunez | TCP/IP Packet Analyzer on a Zynq Platform |
| Dante Casalena; Fabio Federici; Luigi Pomante; Giacomo Valente; Danilo Andreetti; Dario Pascucci | Exploiting Paravirtualization to Support Time and Space Isolation in Multi-Core Platforms for the Avionic Domain |
| Vittoriano Muttillo; Fabio Federici; Luigi Pomante; GiacomoValente; Marco Faccio | Enhancing a FPGA-Based SMP Embedded Platform with OpenMP Support and Unobtrusive System Monitor |
| Gerald Hempel; Markus Vogt; Jeronimo Castrillon; Christian Hochberger | Software-Backed Caching and Virtual Addressing for Generated Accelerators in SoC FPGAs |
| Steffen Thielemans; Maite Bezurnatea; Jaques Tiberghien; Abdellah Touhafi; Kris Steenhaut | Optimising the Reset Functionality of Arduino Boards through Firmware Modification |
| Maite Bezurnatea; Jaques Tiberghien; Kris Steenhaut | Measurement Techniques for an Experimental Wireless Sensor Network Testbed |