My workstation hard drive finally finished testing over the weekend, and I used most of the week to set it up. I made a clean install of Crunchbang Linux, as well as:

• Xilinx ISE Design Suite 14.6 (System Edition) for HDL synthesis;
• Mentor Graphics Questa Advanced Simulator 10.2 for verification; and
• Mathworks MATLAB R2013b and Simulink for data analysis and system simulation.

The remainder of the week was spent building the initial HDL project, using the existing user constraints file. I set up the git repository with a (private) Bitbucket remote, so I can work from elsewhere.

Over the next week, I will get started on the first actual task: building the FSK modem. I will begin by implementing the transmitter, which is easy to test without a receiver, and it will supply enough common scaffolding to speed up later development.