This was a productive week: the modulator was finished and verified, and new symbol mapping, paralleliser, and flow control modules were created. The mapper and parallelliser were also fully verified.

The symbol mapper is, for now, a simple Gray coding module, which may also be disabled to work transparently. If time permits, we will add coding to implement coded (or trellis-coded) modulation and improve multipath resilience.

The flow control module was not in the original architecture, but its need was apparent after considering the interface between a control computer and the modem: data may arrive at arbitrary data rates, but it must be input to the transmitter at a constant (programmable) rate, at or below the maximum possible rate. This is also relevant for symbol timing, since the DDS output must be turned off if there is no more data to transmit.

The implementation of flow control will be done using a FIFO queue (available as an IP core) as a buffer between input and output. This queue has already been synthesised, and clock generator and serialiser modules have also been written and verified to be used in the flow control module. The implementation of this module will be finished and verified over the next week.