This week marks the completion of the first version of the project that’s more than just a brick. The flow control module has been completed and verified, and everything has been integrated into the toplevel for simulation and FPGA implementation. Some changes were needed in the transmitter blocks, mainly to add clocking signals to the mapper and modulator for bit rate control. I also introduced some phase continuity improvements for the transmitter output, so that it drives the transducer as smoothly as possible at the start and end of symbol transmission.

In order to allow actual physical testing, I added a UART for external communication to the toplevel. We decided to use the RTS pin of the serial port to control whether the port was in configuration or data mode, which allows us to defer the implementation of a full protocol until a later stage. The configuration interface is therefore fairly simple, and it’s used only to read or write the configuration registers.

Since building a DAC board for transmission would take some time and effort, we have decided to try using a delta-sigma modulator to directly drive an output pin and feed the transducer driver. The latest behavioural simulations show the full transmitter project is working correctly, but some MATLAB analysis is still necessary to verify that the delta-sigma modulation is good enough for physical implementation.

Finally, I took the weekend to update the website layout. I am now using Hyde, an appropriately named theme for Jekyll. I also redid some of the page organisation, but most of the content remains the same.