Referências

[1] DIGITAL CONTENT PROTECTION. Digital Content Protection for New Home Theater Networking Scenarios, November 2008. URL: http://www.digital-cp.com [último acesso em 2014-12-12].

[2] Ingrid Verbauwhede Alireza Hodjat. Area-Throughput Trade-Offs for Fully Pipelined 30 to 70 Gbits/s AES Processors. IEEE TRANSACTIONS ON COMPUTERS, VOL. 55, NO.4,2006.

[3] Akashi Satoh, Sumio Morioka, Kohji Takano, e Seiji Munetoh. A Compact Rijndael Hardware Architecture with S-Box Optimization. Em Colin Boyd, editor, Advances in Cryptology — ASIACRYPT 2001, volume 2248 de Lecture Notes in Computer Science, páginas 239–254. Springer Berlin Heidelberg, 2001. URL: http://dx.doi.org/10.1007/3-540-45682-1_15.

[4] Karthick Ramu Chethan Ananth. Fully pipelined implementations of AES with speeds exceeding 20 Gbits/s with S-boxes implemented using logic only. Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2001.

[5] P. Maistri e R. Leveugle. 10-Gigabit Throughput and Low Area for a Hardware Implementation of the Advanced Encryption Standard. Em Digital System Design (DSD), 2011 14th Euromicro Conference on, páginas 266–269, Aug 2011. doi:10.1109/DSD.2011.37.

[6] Philippe Bulens, François-Xavier Standaert, Jean-Jacques Quisquater, Pascal Pellegrin, e
Gaël Rouvroy. Implementation of the AES-128 on Virtex-5 FPGAs, volume 5023 de Lecture Notes in Computer Science. Springer Berlin Heidelberg, 2008. URL: http://dx.doi. org/10.1007/978-3-540-68164-9_2.

[7] SYNOPSYS. Corporate Backgrounder, 2014. URL: http://www.synopsys.com/Company/AboutSynopsys/Pages/CompanyProfile.aspx [último acesso em 2014-01-12].

[8] IDC1. Hdmi, the digital display link, December 2006. URL: http://www.hdmi.org/pdf/whitepaper/SilicaonImageHDMIWhitePaperv73(2).pdf [último acesso em 2014-01-29].

[9] FIPS PUBS. ADVANCED ENCRYPTION STANDARD (AES). Relatório técnico, Federal Information Preocessing Standards Publications, November 2001.

[10] Morris Dworkin. Recommendation for Block Cipher Modes of Operation. Relatório técnico, National Institute of Standards and Technology, 2001.

[11] C. Paar e J. Pelzl. The Advanced Encryption Standard(AES). Em Understanding Cryptography, páginas 87–117. Springer-Verlag, 2010.85

[12] Vincent Rijmen. Efficient Implementation of the Rijndael S-box. Proceedings of the 12th
Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2001.

[13] Karim M. Abdellatif, Roselyne Chotin-Avot, e Habib Mehrez. The Effect of Sbox Design on Pipelined AES Using FPGAs. páginas 1–4, Maio 2012. URL: http://www2.lirmm.fr/w3mic/SOCSIP/images/stories/137_GDR_SOC_SIP_The_Effect_of_S-box_Design_on_Pipelined_AES_Using_FPGAs.pdf.

[14] Akashi Satoh, Takeshi Sugawara, e Takafumi Aoki. High-speed Pipelined Hardware Architecture for Galois Counter Mode. Em Proceedings of the 10th International Conference on
Information Security, ISC’07, páginas 118–129, Berlin, Heidelberg, 2007. Springer-Verlag.
URL: http://dl.acm.org/citation.cfm?id=2396231.2396242.

[15] Alireza Hodjat e Ingrid Verbauwhede. A 21.54 Gbits/s Fully Pipelined AES Processor
on FPGA], organization=University of California, Loas Angeles, journal=Proceedings of
the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines,
year=2004.

[16] Lawrence E. Bassham III. The Advanced Encryption Standard Algorithm Validation Suite
(AESAVS). Relatório técnico, Federal Information Preocessing Standards Publications, November 2002.

[17] Leda User Guide, Version I-2014.03.

[18] VCS R /VCSi User Guide, Version l-2014.03-2.

[19] Design Compiler User Guide, Version I-2013.12-SP4.

[20] Formality User Guide, l-2013.12-SP2.

[21] TetraMAX ATPG User Guide, Version I-2013.12-SP4.

[22] PrimeTime User Guide, Version l-2014.03-2.