The information required to generate a test program segment for component test is summarised in table 1.
Due to the simplicity of the internal logic, there are no BIST functions available. However, and precisely because the internal logic consists only of identity functions, it is easy to perform a simple "dead or alive" test. Two test vectors are used for this purpose, toggling each input and applying complementary logic values in adjacent pins. Notice that this simple test does not guarantee that there are no faults present (a short-circuit between input pins 0 and 2, for example, would in this case escape detection), but additional test vectors might be used in situations with higher reliability requirements. The two test vectors, their expected responses and mask data are shown in table 2.
Recall that the sequence of BS cells in each IC, starting from TDI, are those associated to the 2 tristate control pins, the 8 input pins and the 8 output pins. The 8 bit locations following the 2 leftmost bits in the "shift in" column therefore contain the test vector that is to be applied to the internal logic (01010101 and 10101010 respectively). The responses are captured in the 8 rightmost bits, according to the expected responses and mask data presented in table 2.