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• Number and identification of the BS chains that have cells present in this interconnect

Concerning the output pins present:

• Number of output pins and (for each one) location, in the BS chain, of the output cell, the control cell (if any) and the logic value that drives the pin to the high-impedance state.

Concerning the input pins present:

• Number of input pins and (for each one) location, in the BS chain, of the input cell.

Concerning the bidirectional pins present:

• Number of bidirectional pins and (for each one) location, in the BS chain, of the output cell, the input cell, the control cell and the logic value that drives the pin to the high-impedance state.

Concerning the primary input pins present (it is assumed that each primary input pin is driven by an external test channel that enables the primary input to be set to the high-impedance state):

• Number of primary input pins and (for each one) an identification number and the control value that drives the respective test channel to the high-impedance state.

Concerning the primary output pins present:

• Number of primary output pins and (for each one) an identification number.

Finally, and considering the possible case of interconnects that tie unused input pins to ground or VCC:

• Is the interconnect at a fixed logic level and if so at which logic value?

The information required for generating the test program segment concerning the full-BS interconnects, in our demonstration board, is presented in table 1.
 

Table 1: Information required to generate the test program for full-BS interconnects.