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Interconnect test pattern number 7 (last TP for short fault detection):
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Boundary scan chain number 0:
Test pattern:
TP[0][7]:
0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Expected result - shifted out while a following "dummy" TP is shifted in:
ER[0][7]:
0 0 1 0 1 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Mask bits (for this expected result):
MB[0][7]:
1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Boundary scan chain number 1:
Test pattern:
TP[1][7]:
0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 0 0 1
Expected result - shifted out while a following "dummy" TP is shifted in:
ER[1][7]:
0 0 0 0 0 0 0 0 1 0 1 0 0 1 1 0 0 1
Mask bits (for this expected result):
MB[1][7]:
1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0
Primary inputs and corresponding control signals:
PI[7]:
1 0 1 0 1 0 0 1
CS[7]:
1 1 1 1 1 1 1 1
Expected values and masks at primary outputs:
PO[7]:
1 0 0 1 1 0 0 1
POM[7]:
1 1 1 1 1 1 1 1