|Two main types of faults may affect the integrity of the BS
infrastructure: Faulty TAP interconnects (open or short faults in the TDI,
TDO, TMS, TCK or /TRST pins) or faulty / misplaced components. The
sequence of operations usually carried out to detect these faults starts
with the initialisation of the BS logic in each component (the TLR TAP
controller state can be reached from any other state by the application of
a 1 in TMS during not more than 5 TCK cycles), which is followed by:
The IEEE 1149.1 std states that the result of a capture
operation in the IR (taking place in the Capture-IR TAP controller state)
must be X…X01, where X represents a "don’t care" condition
and the rightmost bit is closest to TDO. This feature was defined with the
objective of enabling the simple integrity check operation shown in figure
1, that consists of bringing the TAP controller FSM to the Capture-IR
state and then on to Shift-IR and to scan out the IR contents in all BS
Figure 1: Integrity checking of the BS chain by capture-and-scan through the IRs.
Since the two least significant bits in each IR are 01, every TDO-TDI connection will be forced to 0 and to 1, which enables the detection of a large spectrum of faults in the TAP pins:
Some specific faulty conditions might remain undetected by this simple test, but these situations would normally prevent correct operation in the following steps of the test protocol and as such be rapidly detected (alternatively, a more sophisticated infrastructure test may be specified). An example of one of these specific faults might be a short circuit between TDO and TDI of the same TAP, in a chain where all ICs have the same specification for the IRs. The reader is invited to explain why this particular fault would not be detected by this test and to suggest a way to detect it.
Boards with more than one BS chain may have their BS infrastructures checked independently, but again there are a few specific faults which will only be detected if the integrity check is co-ordinated in all chains. An example of one of these faults might be a short circuit between two TDO pins in different chains, which will be in high-impedance except when scanning is in progress. If one BS chain is in TLR state while the other is being checked, any short-circuit between two TDO pins in different chains has no effect, since only one of them will be active. Again the reader is invited to specify a co-ordinated integrity check procedure that is able to detect the situation referred above for the case of multiple BS chains.
If the capture-and-scan test runs without problems there is a high probability that no faults are present in the BS chain. However, and if there are components supporting the optional IDCODE or USERCODE instructions, it is recommended that these instructions are used to check that the proper components were placed where they are expected to be.