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Once a simple integrity check is concluded with success, the next step consists of checking that open or short circuit faults are not present in the remaining board interconnects. It should be recalled that power has to be applied to the board while testing through the BS chain, meaning that potentially destructive short-circuit currents should be detected as early as possible. In fact, the only two types of tests carried out before looking for short-circuit faults are the BS chain integrity check and the application of test vectors for the detection of open faults, in both cases because of the small number of test vectors involved.

Proceeding to the open fault detection phase is done by shifting into the IRs the SAMPLE / PRELOAD instruction, which selects the BS register in each IC and enables the first vector to be shifted in. Once each output latch in the BS cells has been loaded with the first logic value to be applied to each pin, the EXTEST instruction is shifted into all IRs, forcing the mode multiplexer to decouple the internal logic from the pins and leading to the application of the first vector.

The generation of test vectors to detect open faults in full-BST interconnects is based on the practical experience of dealing with floating inputs (TTL inputs will normally capture a 1 while CMOS inputs are not predictable). Open faults may therefore be detected by driving each interconnect to 0 and checking the value captured at the corresponding input pins, followed by the same operation, but now driving each interconnect to 1. In interconnects with multiple driving pins, as shown in figure 1, detection of all open faults will only be guaranteed if the previous procedure is repeated through each driving pin in turn (the remaining driving pins in the same interconnect will meanwhile be kept in the high-impedance state).

Figure 1: Testing for open faults in interconnects with multiple driving pins.

The number of test patterns required for open fault detection is therefore equal to the double of the maximum number of driving pins existing in a single interconnect, meaning that the number of test vectors required to provide complete open fault coverage is normally very low.