[previous] [next] [contents]    Basic test concepts - Fault modelling and ss@ faults
Our first challenge when trying to classify or enumerate the possible alternatives causing incorrect circuit operation is how to cope with the very large number of different causes leading to this occurrence. Short or open circuits, as well as defective or incorrectly mounted components, are just a few among several other common reasons for circuit malfunction. Considering that short circuits alone grow exponentially with the number of nodes in the circuit, it becomes immediately clear that no feasible test strategy can be developed unless the complexity of the problem is first reduced to acceptable levels.
Confining the boundaries of the test problem, in terms of complexity, will then have to start by reducing the number of situations leading to circuit malfunction. This was the reason why the development of methods to describe physical defects at logic level started as soon as the early 60s, basically when it started to become clear that testing an integrated circuit (IC) could not continue to be done by checking correct operation for all input combinations. Fault models were the result of this effort and enable us to develop test vector generation algorithms without having to consider the unfeasible universe of physical defects, but rather a much smaller group of their "representatives" at logic level. It should however be stressed that there is in fact no "equivalence" relationship between defects and faults, since otherwise the complexity of the problem would basically be the same. The attributes that qualify a good fault model are mainly two, namely:
    1. It has to be sufficiently simple to allow efficient test vector generation procedures
    2. It has to be sufficiently representative in order to guarantee that the percentage of defective components passing undetected (by a test vector set able to detect 100% of the faults) is very small

Among several fault models that were proposed over the years, the single stuck-at (ss@) fault model was one of the first and still is one of the most popular (due to its properties concerning the two attributes defined above). This fault model defines only two types of faults, s@1 and s@0, and considers that only one fault at a time is present in the circuit. Notice that this restriction guarantees that the number of faulty conditions now grows linearly with the number of nodes, instead of exponentially, which enables the development of practical computer programs for automatic test vector generation.
Even without providing a close representation of real manufacturing defects (there is no equivalence between short-circuited nodes and stuck-at nodes), experience has shown that test vector sets approaching 100% fault coverage of ss@ faults are very effective in preventing defective components to pass undetected.