Table of contents
Basic test concepts
        Fault modelling and single-stuck-at (ss@( faults)
        Controllability, observability and testability
        Test vector generation for combinational circuits
        Redundancy and undetectable faults
Scan design techniques
        Testability and test generation in sequential circuits
        Testability improvement via ad hoc solutions
        Structured approaches to DFT
Boundary-scan test
        The BS architecture and test access port (TAP)
        The basic boundary-scan cell
        The test data registers
        The instruction register
        The TAP controller
        Work assignment: Scan Educator and the SN74BCT8244
Test protocol for BS boards
        Fault detection in the BS infrastructure
        Open fault detection in full BST interconnects
        Short circuit detection among full BST interconnects
        Full BST interconnect testing with multiple BS chains
        Fault detection in non-BS clusters
        Testing non-BS clusters with multiple BS chains
        Detection of faulty components
A BS test controller model
        Classification of test operations
        Control of the BS infrastructure
        Synchronisation of the BS infrastructure with external test resources
        Control of internal resources and test program flow
        The test instruction set
        Scope of the proposed BS test controller model
Case-study: Test program generation for an 1149.1 board
        The demonstration board
        Information required to test the BS infrastructure
        Information required to test the full BST interconnects
        Information required to test the non-BS clusters
        Information required to test the BS components
        Test vectors for short circuit detection in full BST interconnects
        The complete set of test vectors, expected responses and mask data
        The test program
JTAGer: A Windows BS test controller application
        Set up information
        Control bar
        Status information
        Syntax rules
        Windows menu - State diagram
        Windows menu - Waveforms
        Windows menu - Event list
        Windows menu - Show parallel port signals
        Utilities menu - Bitstream shifter
        Utilities menu - Received bitstream viewer
        Utilities menu - Use parallel port
        Application example
The IEEE 1149.4 std for mixed-signal test
        1149.4: An extension of 1149.1
        The basic 1149.4 architecture
        The test register structure
        1149.4 instructions
        The Test Bus Interface Circuit (TBIC)
        The TBIC switching structure
        The Analog Boundary Modules (ABM)
        The ABM switching structure
        Interconnect testing with 1149.4
        Short-circuit detection with 1149.4
        Basic analog test operations
        Impedance measurement (pin to ground)
        Functional description of a basic 1149.4 component
        Implementation of the 1149.4 demo "component"
        Proposed experiments with the 1149.4 "component"