|The BS test controller model presented in
this section comprises a reduced number of instructions belonging to the
three types described. This instruction set enables us to specify test
programs for any board with one or two BS chains, with or without non-BS
clusters, provided that no more than two synchronisation channels are
required to apply / capture test vectors / responses to the board primary
I/O pins or cluster I/O pins.
The instruction set proposed has a very low abstraction level, meaning that test program generation is a tedious and error-prone task if done manually. The ideal situation would naturally be that an automatic test program generation tool is used to produce the test program for each case, from a set of input files containing the board structural information (netlist), the description of the BS architecture in each BS IC and the external test vector sets for non-BS clusters testing.
However, we must recall that the proposed test controller model has a pedagogical objective that would not be achieved if the small details of controlling the BS chain at bit-level were omitted.