|According to the basic test operations that
were previously identified, this section presents the instruction set of
our BS test controller. Formal specification of any test program becomes
possible with this instruction set, as will be seen when a case study with
two BS chains and non-BS clusters is presented in a later chapter. The BS
test controller instruction set is presented in three parts, each
addressing the basic test operation types that were described earlier.
Control of the BS infrastructure
The instructions available to control the BS infrastructure are those presented in table 1, assuming that the board under test may have one or two BS chains. The mnemonic and a simplified description of its operation are presented for each instruction.
Timing specifications will not be presented here, since these details depend on each possible implementation of the BS test controller model. At this stage we are only interested in presenting a functional model of the test controller, which enables us to code the test protocol steps.
NSHCP shifts a new bitstream into the selected BS chain, but at the same time compares the bitstream shifted out with possible expected results, whenever they are known (in some - or most - bit positions we may not know what will come out). As such, this instruction requires the following arguments:
These bit streams will be presented in hexadecimal form, starting with the most significant (leftmost) bit. The small example shown in figure 1 may help to clarify the proposed rule to build the bit stream of the NSHFCP instruction, assuming that we want to:
Figure 1: A simple 16-bit BS chain.
The NSHFCP instruction bit stream would in this case be as follows:
The first group of digits (5500H) represents the 16-bit test vector to be shifted in (starting by the leftmost bit, which at the 16th TCK cycle will arrive in cell 15). The second group (0309H) represents the expected values for all 16 bit positions (the leftmost bit represents the expected value for cell 15). However, and since we do not have expected values for every bit that will be shifted out, the third group of digits specifies which positions are to be considered for comparison purposes (the leftmost bit represents the mask information for cell 15 - in our case it is 0, since we do not know the expected value for this position).
Synchronisation with external test resources
Table 2 presents the instructions for synchronisation with external test resources, assuming the availability of two synchronisation channels (A and B).
Control of internal resources and test program flow
The instructions available for controlling internal resources and test program flow are shown in table 3, assuming the existence of eight error flags per BS chain.
Our test controller model assumes that the LD CNT,N instruction has to be included before the following instructions: NTCK, NSHF and NSHFCP. Naturally, there would be alternative ways to specify the number of TCK cycles required (and we might even argue that NSHF and NSHFCP should not require to be preceded by LD CNT,N because the number of TCK cycles required is simply the number of bits in the respective bit streams). However, we must keep in mind our objective of presenting a test controller model that makes no assumptions restricting the possible implementation alternatives, which in the case of a dedicated test controller chip would have the bit streams following the NSHF / NSHFCP opcodes stored in memory and could not therefore know how many TCK cycles were required.