|The basic 1149.4 architecture may be represented as
illustrated in figure 1, where the four additional structures referred
above are shown.
Figure 1: The basic 1149.4 architecture.Each analog I/O pin has an associated ABM that provides extended controllability and observability operations, enabling interconnect testing and certain types of parametric testing operations. Notice also that ABMs and DBMs are serially connected in an extended boundary scan (BS) register, which also includes cells belonging to the TBIC (as will be described later). Apart from the additional structures referred, the overall test architecture is clearly identical to 1149.1, as would be expected.
The operation of the 1149.4 infrastructure may be exemplified as follows: