Ad hoc measures to improve testability, as the name suggests, consist of design
rules or amendments introduced to avoid test vector generation problems. These
measures are specific to each design and therefore have two major drawbacks:
- Are not always reusable, since each design has its specific requirements
and testability problems.
- Are not able to guarantee high testability levels regardless of the
circuit.
A large number of examples might be used to illustrate ad hoc design for
testability (DfT) rules, but it is largely preferable that structured DfT
rules (considered in the following section) are used instead and as such we will
only refer the following common solutions:
- In order to avoid having to apply a large number of clock cycles to
counters with a large number of bits, it is common to provide a way to split
an n-bit counter into k (n/k)-bit counters for test purposes, which could
then be taken to any n-bit combination with a much smaller number of clock
cycles.
- The provision of reset or preset lines, synchronous or asynchronous, are
also common solutions to force the circuit to one or more given states with
few or even no clock cycles being required.
- In order to enable better observability, some internal nodes may be
brought to primary output nodes, either by increasing the number of these
nodes or by multiplexing existing primary outputs with the internal nodes to
be observed. A similar solution is possible concerning controllability of
internal nodes, which may be connected to additional primary inputs
multiplexed with the internal signals controlling those nodes.
These and other measures are however not systematic enough as to enable a
uniform approach to testable circuit design, which led since the mid-70s to the
development of design methodologies that can always guarantee high levels
of testability.
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