The basic concept underlying most structured design for testability (DfT)
methodologies consists of providing a systematic way of forcing the circuit
to any given state in a fixed (and short) number of clock cycles, regardless
of the current state and of the fault present in its combinational circuitry
(even if affecting the next-state generation logic). The expression structured
DfT implies that the same design approach can always be used and assure
good testability levels, regardless of the circuit function. There is
however a price to pay, which normally consists of accepting that some
design rules (rather a design style) are enforced and that additional
silicon area and propagation delays are tolerated.
Figure 1: Scan design principle.
When each D-FF in the circuit is preceded by this 2:1 multiplexer (creating what is commonly called a scan flip-flop) we have a case of full-scan design. This structured DfT methodology started to gain wide acceptance in the late 70s, when it became evident that test vector generation algorithms for sequential circuits would not be able to cope with the increasing complexity of emerging VLSI designs. Scan design techniques overcome this difficulty by providing a simple solution to the two main problems that make test vector generation for sequential circuits so much complex:
First problem: Part of the combinational circuitry inputs are
not directly controllable, since they come from the D-FF outputs (these
nodes define the circuit present state).
Figure 2 shows the example of taking the circuit to state 110,
assuming that the current state was 100 and that the next state
inputs were 001 (notice again that this sequence is always possible,
regardless of the whatever function the circuit performs or wherever the
fault s@ is located):
Initial circuit conditions: Present state 100, next state 001.
Recall that the present state nodes are (internal) inputs of the combinational
logic block defining the global sequential circuit function and that the
next state nodes are (also internal) outputs of this same block.
The Test Mode control signal is now at 1 and the D-FFs are connected
as a shift-register. The first clock cycle applied will shift the D-FFs
one bit position "up" and transfer the value present at the
Scan In input to the output of the first D-FF in the chain.
The values shown at each node are now those following the application
of the second clock cycle, keeping Scan In at 1.
The last clock cycle has now been applied with the Scan In input set
at 0, so the new present state is 110 as requested.
The requested present state has been loaded and the Test Mode control
signal has been taken back to 0.
Second problem: Part of the combinational circuitry outputs are
not directly observable, since they go to the D-FF inputs (these nodes
define the circuit next state).
Figure 3 considers the same initial conditions as in figure 2.(a) and
shows how to observe the next state defined by the combinational circuitry
outputs (again whatever the circuit function, wherever the fault may be):
The initial circuit conditions are the same as in the previous example,
the present state being 100.
The values shown at each node are those following the application of
the first clock cycle. Since the Test Mode control signal was kept at
0, the values transferred to the D-FF outputs were those present
in the next state nodes, defined by the (internal) outputs of the combinational
logic block. Notice that the value present at the Scan Out output is now
the first bit (leftmost) requested to be shifted out.
The Test Mode control signal was now set to 1 and the values shown
at each node are those following the application of the second clock cycle.
Since the D-FFs are now connected as a shift-register, the present state
nodes were shifted one bit position "up" and the second bit
was shifted out.
The values now shown are those following the application of the third
(and last) clock cycle. The last bit (the rightmost bit in the initial
001 next state) was now shifted out.
Setting the Test Mode control signal to 0 brings the circuit back
to the normal operation mode.
Figure 3: Observability of the next state nodes.
The main virtue of scan design techniques is therefore their ability to eliminate the sequential nature of the circuit, which is seen by the test vector generation tool as a pure combinational circuit. The remarks initially made concerning the cost of DfT should be clear by now:
In those cases where full-scan can not be accepted, it is still possible to select only those nodes which present higher testability problems and use scan flip-flops in those circuit areas.