The ss@ fault model and several improvements over the basic D-algorithm described in
the previous section led to several tools that are very efficient (in terms of execution
time and fault coverage) for test pattern generation, as far as combinational circuits are
concerned. Sequential circuits are however much more difficult to handle in this respect,
for reasons which are better explained through a simple example such as the one shown in
Figure 1: Simple sequential circuit with a s@0 fault.
The problem in this case is that the inputs of the combinational block are connected to the outputs of the flip-flops (the state variables) and not to the circuit primary inputs. What we got as a result of the D-algorithm procedure was therefore the state combination that is required to detect X s@0, but the sequence in A that will bring the circuit to this state is still to be found. In the example of figure 1 this is not really a problem, since two clock cycles with A=1 will bring the two flip-flop outputs to 1 (and their complements to 0), as the user may confirm using the interactive schematic diagram presented in figure 2.
Figure 2: Interactive schematic diagram of a simple sequential circuit.
The following remarks will help us to understand why test generation for sequential circuits is generally a very complex problem (and why it was not so for the case considered in figure 1):
Considering a fault that modifies the state transition diagram will give us a better understanding of how difficult it will become to find a test vector, even for the very simple circuit shown in figure 1. The case of node Y s@0 is one of such faults, since we can no longer in this case continue to consider the fault-free state transition diagram. Figure 3 shows the two diagrams for this case, assuming that Q1 and Q0 are respectively the outputs of the upper and lower flip-flops.
Figure 3: State transition diagram for the circuit of figure 1, with and without Y s@0.
As we already know, setting A=1 during two clock cycles takes the circuit to state 3 and enables the detection of X s@0 (Q1,Q0=11 as shown in figure 3.(a)). However, if Y is s@0, the new steps required to detect this fault will have to be as follows:
It is interesting to notice that the same sequence in A (1 during two clock cycles) will also detect Y s@0, as becomes evident by considering the state diagrams shown in figure 3. The circuit will be taken to state 3 if the fault is not present (F=1) and will otherwise remain in state 0 (F=0) if Y is s@0.