[previous] [next] [contents]    Scan design techniques - Testability and test generation in sequential circuits

The ss@ fault model and several improvements over the basic D-algorithm described in the previous section led to several tools that are very efficient (in terms of execution time and fault coverage) for test pattern generation, as far as combinational circuits are concerned. Sequential circuits are however much more difficult to handle in this respect, for reasons which are better explained through a simple example such as the one shown in figure 1.
The application of the basic D-algorithm procedure to the case of fault s@0 in node X rapidly leads us to the test vector required at the inputs of the combinational block (the two ANDs and one OR), but these are not the circuit primary inputs. In fact, our circuit is seen from the outside as having only one primary input (A) and one primary output (F), besides the clock signal.

Figure 1: Simple sequential circuit with a s@0 fault.

The problem in this case is that the inputs of the combinational block are connected to the outputs of the flip-flops (the state variables) and not to the circuit primary inputs. What we got as a result of the D-algorithm procedure was therefore the state combination that is required to detect X s@0, but the sequence in A that will bring the circuit to this state is still to be found. In the example of figure 1 this is not really a problem, since two clock cycles with A=1 will bring the two flip-flop outputs to 1 (and their complements to 0), as the user may confirm using the interactive schematic diagram presented in figure 2.

Figure 2: Interactive schematic diagram of a simple sequential circuit.

The following remarks will help us to understand why test generation for sequential circuits is generally a very complex problem (and why it was not so for the case considered in figure 1):

  1. The application of the D-algorithm gives us the combination required at the inputs of the combinational block, which include the flip-flop outputs, but the sequence required at the primary inputs to reach this state is still to be found and requires knowledge about the circuit state transition diagram. This was not a problem in the example of figure 1 because the two flip-flops are connected as a shift-register and therefore it is very straightforward to load any required state at their outputs.
  2. Even when the fault-free state transition diagram is known beforehand, it may well happen that a ss@ fault affects the next state outputs of the combinational block. In this case the new state transition diagram would have to be computed before the sequence required at the primary inputs can be found. Again this was not the case in the example of figure 1, where the fault at node X has no such effect.

Considering a fault that modifies the state transition diagram will give us a better understanding of how difficult it will become to find a test vector, even for the very simple circuit shown in figure 1. The case of node Y s@0 is one of such faults, since we can no longer in this case continue to consider the fault-free state transition diagram. Figure 3 shows the two diagrams for this case, assuming that Q1 and Q0 are respectively the outputs of the upper and lower flip-flops.

(a) Fault-free operation.

(b) Node Y s@0.

Figure 3: State transition diagram for the circuit of figure 1, with and without Y s@0.

As we already know, setting A=1 during two clock cycles takes the circuit to state 3 and enables the detection of X s@0 (Q1,Q0=11 as shown in figure 3.(a)). However, if Y is s@0, the new steps required to detect this fault will have to be as follows:

    1. The D-algorithm will give us the required test vector at the inputs of the combinational block (same as for X s@0).
    2. The new state diagram for the faulty circuit, shown in figure 3.(b), will now have to be derived (this step was not necessary for the case of X s@0).
    3. Analysing the two state diagrams, we are now finally able to find out the required sequence at primary input A (this is again the same as for X s@0, except that we do not use the fault-free state diagram).

It is interesting to notice that the same sequence in A (1 during two clock cycles) will also detect Y s@0, as becomes evident by considering the state diagrams shown in figure 3. The circuit will be taken to state 3 if the fault is not present (F=1) and will otherwise remain in state 0 (F=0) if Y is s@0.