Compilation for Embedded Reconfigurable Computing Architectures

Pedro C. Diniz1, and João M. P. Cardoso2[i]

1 Departamento de Engenharia Informática, IST/UTL/INESC-ID, Lisboa, Portugal

2 Departamento de Engenharia Informática, FEUP/Universidade do Porto, Porto, Portugal,

http://www.fe.up.pt/~jmpc

jmpc@acm.org

Based on the short-tutorial given at:

3rd Summer School on Generative and Transformational Techniques in Software Engineering (GTTSE’09), 6–11 July, 2009, Braga, Portugal, http://gttse.wikidot.com/2009

Abstract. Embedded Systems permeate all aspects of our daily life, from the ubiquitous mobile devices (PDAs or smart-phones) to play-stations, set-top boxes, household appliances, and in every electronic system, be it large or small (e.g., in cars, wrist-watches). Most embedded systems are characterized by stringent design constraints such as reduced memory and computing capacity, severe energy consumption limitations, weight and space limitations as well as short life and, most importantly, strict design cycles.  Reconfigurable technology as emerged as a key technology for embedded systems as it offers the promised of increased system performance and component number reduction including components that can be customized or specialized (even dynamically) to the task at hand. A system might execute specific tasks more efficiently via dynamic reconfiguration thus reducing the weight and power used for a particular computation. Reconfigurability, however, exacerbates the complexity of compiling high-level languages to these systems, which prompted various research projects to tackle this hot-topic of research. In this tutorial, we begin by presenting and discussing current compilation techniques for traditional embedded systems highlighting key high-level design issues. In a second phase, we present the role of specific compiler techniques when targeting embedded systems including a microprocessor, with customized functional units, or tightly coupled with reconfigurable functional units (i.e., functional units that can be customized to compute certain parts of an application). In this context, we focus on the issues of dynamic reconfiguration, temporal and spatial partitioning and custom functional unit synthesis. Given the tremendous growth of Field-Programmable Gate-Arrays (FPGAs) and their ability to emulate in a very flexible fashion embedded systems-on-a-chip, we will focus on compilation techniques that are particularly suited to these devices. In particular, we cover important analysis and mapping techniques for high-level imperative programming languages to FPGAs, seen by many as an enabling technology for reconfigurable embedded architectures.

Presentations

Quick INTRO

Tutorial, Part A

Tutorial, Part B

Additional Material

From Load/Store to Streaming

Smooth Data Reuse Example

Software for Smooth Image Processing Example (Java source and classfiles)

MAINLY Based on the Bibliography

·         João M. P. Cardoso, and Pedro C. Diniz, Compilation Techniques for Reconfigurable Architectures, Springer, 234 p., October 2008, ISBN 978-0-387-09670-4.

·         João M. P. Cardoso, João Bispo, and Adriano K. Sanches, “Mapping Programming Models to Reconfigurable Computing Platforms,” Chapter in the book: Behavioral Modeling for Embedded Systems and Technologies: Applications for Design and Implementation, Luís Gomes, João M. Fernandes (eds.), IGI Global, July 2009.

Ó João M. P. Cardoso and Pedro C. Diniz



Short Bios

Pedro C. Diniz, graduated from the Technical University of Lisbon in Portugal where he got his BSc and MSc in Electrical Engineering. In 1997 he got his PhD in Computer Science from the University of California, Santa Barbara in Parallelizing Compilers. In 1997, he joined the University of Southern California’s Information Sciences’ Institute (USC/ISI) where he worked on the application of compiler techniques to the problem of automatic mapping of computation expressed in high-level imperative programming languages, such as C, to configurable computing architectures such as Field-Programmable-gate-Arrays (FPGAs). He is currently working on extending this compilation work to emerging configurable architectures with heterogeneous and programmable resources, such as hardware multipliers and RAM blocks. He has participated in the organization of a number of conferences (FPL, ARC, RAW) and he regularly serves as a Program Committee member for various international conferences (e.g., PLDI’09, EuroPar’09). He is co-author of a Springer book and co-editor of three Springer LNCS volumes. He has (co-)authored over 80 scientific publications (including journal/conference papers and patents) on subjects related to compilers, embedded systems, and reconfigurable computing. He is a member of IEEE, IEEE Computer Society.

 

João M. P. Cardoso, got a 5-year Telecommunications and Electronics Engineering degree from the University of Aveiro in 1993, and an MSc and a PhD degree in Electrical and Computer Engineering from the IST, Lisbon, Portugal in 1997 and 2001, respectively. He is currently Associate Professor at the Department of Informatics Engineering, Faculty of Engineering of the University of Porto. Before, he was with the IST/Technical University of Lisbon (2006-2008), a senior researcher at INESC-ID (2001-2009), and with the University of Algarve (1993-2006). In 2001/2002, he worked for PACT XPP Technologies, Inc., Munich, Germany. He has participated in the organization of a number of conferences (FPL’03-08, ARC’05-07) and he serves as a Program Committee member for various international conferences (e.g., IEEE FPT, FPL, IC-SAMOS, ACM SAC, ARC, ARCS, DIPES, IEEE SASP). He is co-author of a Springer book and co-editor of two Springer LNCS volumes. He has (co-)authored over 70 scientific publications (including journal/conference papers and patents) on subjects related to compilers, embedded systems, and reconfigurable computing. He is a member of IEEE, IEEE Computer Society and ACM.