FPGA Design Contest

An FPGA design contest for groups of undergraduate students will take place on the first day of REC 2011.

The participating groups will receive the specification of the design at the start of the contest, and they will have the rest of the day to design and implement the corresponding system.

All groups will use the same resources (provided by the organization):

  • a personal computer with Xilinx ISE (10.1 or 11.1) and Modelsim 6 simulator;
  • a board with a Xilinx Spartan 3/3E FPGA.

The winner will be the first group to present a complete implementation of the system. The winning group will make a presentation of their work on the following day, just before the closing session of REC 2011.


The winning team will receive a Nexys-2 Spartan 3E 1200 board from the sponser of the competition Trenz Electronic.

Logo of Trenz Electronic
FPGA and ARM board supplier,European Partner of Digilent

The winners will have the opportunity of presenting their project on the last day of REC 2011.

Design description

All designs will address the same task, which will be presented in a briefing the beginning of the competition. Development will be done using the basic design tools from Xilinx (ISE), without other high-level development tools. Designs can be specified in Verilog or VHDL.

Teams will receive an ISE project containing the top-level definitions of the FPGA platform. The project includes a top level module that connects the I/O signals of the design to the peripherals available on the platform and to the I/O connectors relevant for the competition. The top level module will be made available in Verilog and VHDL.

In order to help the teams prepare for the competition, a description of some of the characteristics of the task to be addressed follows:

  • The system will calculate the values of some physical quantities based on data acquired from sensors. Data acquisition will require measuring the time between transitions of digital signals.
  • Communications with a host computer will use a serial interface (RS232) with 115200 bps, 8 bits/char, no parity. Data will be sent as ASCII characters representing integer decimal values.
  • The same serial interface will be used to configure the operation of the system using a small set of commands (in ASCII).


  1. Groups will have at most four undergraduate students.
  2. The contest runs without interruption from 10:30 to 18:30 on 3 February 2011.
  3. Groups will use only the resources provided by the organization.
  4. The system must be designed and implemented wholly during the contest.
  5. The organization will provide a simulation testbench covering the basic functionality.
  6. The first group to submit a design that complies with the specification will be the winner.
  7. Compliance will be checked automatically by a test system.
  8. Any situations not covered by the rules will be analyzed by the jury of the contest. All jury decisions are final.

Registration for the contest

In order to register for the competition, groups should fill the application form and send it by email to rec2011@fe.up.pt using the subject line Competição REC2011.

The number of groups is limited. Applications will be processed in incoming order.

The deadline for registration for the contest is 14 January 2011.

Registration for the contest does not require registration for the technical sessions of REC 2011.


José Carlos Alves (FEUP/INESC Porto)