EU-Funded Projects Special Session
This session will have presentations about projects funded by the European Union.
April 15 (Tuesday), 10:45 - 12:30, Session T1
Session Chair: M.D. Santambrogio, Politecnico di Milano, Italy
I. Sourdis, C. Strydis, A. Armato, C.S. Bouganis, B. Falsa, G.N. Gaydadjiev, S. Isaza, A. Malek, R. Mariani, S. Pagliarini, D. Pnevmatikatos, D.K. Pradhan, G. Rauwerda, R.M. Seepers, R.A. Shak, G. Smaragdos, D.Theodoropoulos, S. Tzilis, and M. Vavouras
Title: DeSyRe: on-demand Adaptive and Recongurable Fault-tolerant SoCs?
Ioannis Sourdis is an Assistant Professor in Computer Engineering at Chalmers University of Technology, Sweden. He has an engineering diploma Dipl-Eng ('02) and a MSc ('04) in electronic and computer engineering from the TU Crete, Greece, and a PhD ('07) in computer engineering from TU Delft, The Netherlands. His research interests include architecture and design of computer and networking systems, reconfigurable computing, interconnection networks and multiprocessor parallel systems, fault-tolerant computing and energy-aware computing.
From 2007 until 2010, Sourdis participated in the coordination of the HiPEAC NoE cluster on Reconfigurable Computing. He has co-authored about 35 papers in Int. conferences and journals, cited in over 800 papers. He is participating in the technical committees of 14 Int. conferences; he is reviewer in 21 Int. journals and more than 30 Int. conferences. Sourdis holds a patent in an address lookup technique for network routing. He participated in the Pro3, EASY, SARC and HiPEAC European projects currently participates in the EMC2 Artemis project, and since 2011 coordinates the DeSyRe FP7 project. He is also member of the HiPEAC NoE, member of the management committee of the MEDIAN Cost Action, member of IEEE and ACM.
The DeSyRe project builds on-demand adaptive, reliable
Systems-on-Chips. In response to the current semiconductor technology
trends that make chips becoming less reliable, DeSyRe describes a new
generation of by design reliable systems, at a reduced power and performance cost. This is achieved through the following main contributions.
DeSyRe defines a fault-tolerant system architecture built out of unreliable components, rather than aiming at totally fault-free and hence more
costly chips. In addition, DeSyRe systems are on-demand adaptive to various types and densities of faults, as well as to other system constraints
and application requirements. For leveraging on-demand adaptation/customization and reliability at reduced cost, a new dynamically reconfigurable substrate is designed and combined with runtime system software
support. The above define a generic and repeatable design framework,
which is applied to two medical SoCs with high reliability constraints and
diverse performance and power requirements.
One of the main goals of
the DeSyRe project is to increase the availability of SoC components in
the presence of permanents faults, caused at manufacturing time or due
to device aging. A mix of coarse- and fine-grain reconfigurable hardware
substrate is designed to isolate and bypass faulty component parts. The
exibility provided by the DeSyRe reconfigurable substrate is exploited
at runtime by system optimization heuristics, which decide to modify
component configuration when a permanent fault is detected, providing
D. Pnevmatikatos, T. Becker, A. Brokalakis, G. Gaydadjiev, W. Luk, K. Papadimitriou, I. Papaefstathiou, O. Pell, C. Pilato, D. Pau, M. D. Santambrogio, D. Sciuto, and D. Stroobandt
Title: Effective Reconfigurable Design: the FASTER Approach
Kyprianos Papadimitriou is a Research Associate at the Computer Architecture and VLSI Systems Laboratory of the Institute of Computer Science, FORTH, Crete. He also works as Scientific Staff at the School of ECE of the Technical University of Crete. He received his Diploma and MSc in Electronic and Computer Engineering from the Technical University of Crete, in 1998 and 2003 respectively.
During 1998-1999 he was with the R&D department of ATMEL working on hardware implementation of wireless protocols. In 2003 he co-initiated an effort to establish a spin-off company involved with motion recognition technologies. In 2012 he was granted with a Ph.D from the School of ECE, Technical University of Crete, with a special focus on reconfigurable computing. He is currently working for the FASTER project and has formerly participated in several European and national research projects.
While fine-grain, reconfigurable devices have been available
for years, they are mostly used in a fixed functionality, "asic-replacement"
manner. To exploit opportunities for
exible and adaptable run-time
exploitation of fine grain reconfigurable resources (as implemented currently in dynamic, partial reconfiguration), better tool support is needed.
The FASTER project aims to provide a methodology and a tool-chain
that will enable designers to efficiently implement a reconfigurable system
on a platform combining software and reconfigurable resources.
from a high-level application description and a target platform, our tools
analyse the application, evaluate reconfiguration options, and implement
the designer choices on underlying vendor tools. In addition, FASTER
addresses micro-reconfiguration, verification, and the run-time management of system resources. We use industrial applications to demonstrate
the effectiveness of the proposed framework and identify new opportunities for reconfigurable technologies.
José G.F. Coutinho, Oliver Pell, Eoghan O'Neill, Peter Sanders, John McGlone, Paul Grigoras, Wayne Luk and Carmelo Ragusa
Title: HARNESS Project: Managing Heterogeneous Compute Resources for a Cloud Platform
Jose Gabriel de Figueiredo Coutinho is an associate researcher working in the Custom Computing Research Group at Imperial College London. He received his M.Eng. degree in Computer Engineering from Instituto Superior Tecnico, Lisbon, Portugal in 1997. From 2000 and 2007 he received his M.Sc. and PhD in Computing Science from Imperial College London. Since 2005, he has been involved in UK and EU research projects such as Ubisense, hArtes, REFLECT and HARNESS. His main interests include mapping and optimising high-level descriptions to heterogeneous reconfigurable platforms and aspect-oriented design. He has published over 40 research papers in peer-referred journals and international conferences and has contributed to two book publications.
Most cloud service offerings are based on homogeneous commodity resources, such as large numbers of inexpensive machines interconnected by off-the-shelf networking equipment and disk drives, to
provide low-cost application hosting. However, cloud service providers
have reached a limit in satisfying performance and cost requirements for
important classes of applications, such as geo-exploration and real-time
The HARNESS project aims to fill this gap by developing architectural principles that enable the next generation cloud platforms to incorporate heterogeneous technologies such as reconfigurable
Dataflow Engines (DFEs), programmable routers, and SSDs, and provide
as a result vastly increased performance, reduced energy consumption,
and lower cost profiles. In this paper we focus on three challenges for
supporting heterogeneous computing resources in the context of a cloud
platform, namely: (1) cross-optimisation of heterogeneous computing resources, (2) resource virtualisation and (3) programming heterogeneous
G. Durelli, M. Coppola, K. Djafarian, G. Kornaros, A. Miele, M. Paolino, O. Pell, C. Plessl, M.D. Santambrogio, and C. Bolchini
Title: SAVE - Towards Efficient Resource Management in Heterogeneous System Architectures
Gianluca Durelli received his Bachelor and Master of Science in Computer Engineering from the Politecnico di Milano respectively in September 2009 and April 2012. He is currently in his second year of Ph.D. in Computer Science at the Politecnico di Milano and his research focuses on self-adaptive systems for heterogeneous computing platforms.
During his first year as a Ph.D. student he did an internship at IBM T.J. Watson Research Center working in the High Performance Analytics group.
The increasing availability of different kinds of processing
resources in heterogeneous system architectures associated with today’s
fast-changing, unpredictable workloads has propelled an interest towards
systems able to dynamically and autonomously adapt how computing
resources are exploited to optimize a given goal. Self-adaptiveness and
hardware-assisted virtualization are the two key-enabling technologies
for this kind of architectures, to allow the efficient exploitation of the
available resources based on the current working context.
project will develop HW/SW/OS components that allow for deciding at
runtime the mapping of the computation kernels on the appropriate type
of resource, based on the current system context and requirements.
G. Massari, E. Paone, M. Scandale, P. Bellasi, G. Palermo, V. Zaccaria, G. Agosta, W. Fornaciari, C. Silvano
Title: Data Parallel Application Adaptivity and System-Wide Resource Management in Many-Core Architectures
Gianluca Palermo received the M.S degree in Electronic Engineering, in 2002, and the Ph.D degree in Computer Engineering, in 2006, from Politecnico di Milano. He is currently an assistant professor at Department of Electronics and Information Technology in the same University. Previously he was also consultant engineer in the Low Power Design Group of AST - STMicroelectronics working on network on-chip and research assistant at the Advanced Learning and Research Institute (ALaRI) of the Università della Svizzera italiana (Switzerland).
He has actively participated in several EU-research projects. Since 2003, he published over 100 research papers in international conferences and journals. His research interests include design methodologies and architectures for multi-core embedded systems.
From Introduction of the paper
Since the silicon technology entered the many-core era, new computing platforms
are exploiting higher and higher levels of parallelism. Thanks to scalable, clustered architectures, embedded systems and high-performance computing (HPC)
are rapidly converging. We are also experiencing a rapid overlapping of the challenges related to efficient exploitation of processing resources. Platform-specific
optimization and application boosting cannot be considered independently anymore. Thus the increased interest towards broader and versatile methodologies,
which could easily scale from the embedded up to the general-purpose domain.
[...] This paper proposes an innovative methodology, defined during the 2PARMA
project, based on a properly defined run-time support to enable an effective
exploitation of design-time information. The synergy between design-time and
run-time provides an efficient yet portable run-time management solution which
could scale from embedded to general purpose systems. The methodology proposes the integration of independent tools to provide effective compilation of
OpenCL code, multi-objective design space exploration, system-wide run-time
resource management and application-specific monitoring and tuning [...].