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   Submission deadline
25 October 2013
Abstracts due Nov. 4, 2013
Papers due Nov. 11, 2013 (strict deadline)
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6 December 2013
9 December 2013
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3 January 2014
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21 February 2014
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21 February 2014
   Conference date
14-16 April 2014

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Keynote Speaker

April 14 (Monday), 09:00 - 10:00

Giovanni De Micheli
Professor, IEEE Fellow, ACM Fellow
Institute of Electrical Engineering and of the Integrated Systems Centre
EPF Lausanne

Title: Technologies and Platforms for Cyberphysical Systems


Much of our economy and way of living will be affected by nanotechnologies in the decade to come and beyond. Mastering materials at the molecular level and their interaction with living matter opens up unforeseeable horizons. This talk deals with how we will conceive, design and use cyberphysical systems exploiting devices at the edge of the scaling limits. Whereas switching circuits and microelectronics have been the enablers of computer and communication systems, new nano-devices have the potentials to realize innovative computational fabrics whose applications require broader hardware abstractions. Indeed, new electronic devices act as atomic comparators, rather then switches. On this basis, a new flavor of circuit and logic synthesis is possible and effective.

In the second part of my talk I will address scaling of computing systems, and the current trend to manycore systems. Design complexity and usability will depend much on the interconnection schemes among computational elements. The technological feasibility envelope and the related multivariate design optimization problems find solutions in the network-on-chip choice as a general paradigm for circuit core interconnection.

Last I will describe cyberphysical system applications within the frame of the Swiss nano-tera.ch program. I will address the opportunities and limitations of current computing and communication systems toward addressing problems related to health management and environmental protection.


Giovanni De Micheli is Professor and Director of the Institute of Electrical Engineering and of the Integrated Systems Centre at EPF Lausanne, Switzerland. He is program leader of the Nano-Tera.ch program. Previously, he was Professor of Electrical Engineering at Stanford University.

He holds a Nuclear Engineer degree (Politecnico di Milano, 1979), a M.S. and a Ph.D. degree in Electrical Engineering and Computer Science (University of California at Berkeley, 1980 and 1983). Prof. De Micheli is a Fellow of ACM and IEEE and a member of the Academia Europaea. His research interests include several aspects of design technologies for integrated circuits and systems, such as synthesis for emerging technologies, networks on chips and 3D integration.

He is also interested in heterogeneous platform design including electrical components and biosensors, as well as in data processing of biomedical information. He is author of: Synthesis and Optimization of Digital Circuits, McGraw-Hill, 1994, co-author and/or co-editor of eight other books and of over 500 technical articles. His citation h-index is 81 according to Google Scholar. He is member of the Scientific Advisory Board of IMEC and STMicroelectronics.

Invited Speaker from Industry

April 15 (Tuesday), 09:00 - 10:00

Giulio Corradi
Xilinx Inc.

Title: How to achieve IEC61508 Functional Safety and Security with FPGA and ZYNQ; architectures, methods and tools


Functional safety applications are in growing demand and Xilinx FPGA technology offers a viable solution especially when significant performances are involved. This paper presents several architectures and methodologies for designing SIL2 and SIL3 applications targeting up hardware fault tolerance HFT=1 based on recent silicon products Series 6, Series 7 and ZYNQ-7000®.

Starting with published FIT values the presentation will explore tools methods, as area partitioning, design preservation, partial reconfiguration, isolation design flow, essential and critical bit masking and faults injection, and related methods to achieve the desired SIL level. Structural methods will be presented as a mean of testing on-line the functionality to increase the coverage using internal resources.

System on chip architectures like ZYNQ-7000® offers new options using to implement diverse channels and heterogeneous architectures to mitigate common cause failures will be covered in the paper. The analyzed architectures like lock-step, check pointing and virtualization will be addressed for covering also the application dependent parts. Security breaching is becoming a great concern for industrial product and such threats are now part of the initiator events lists, the paper presents methods, functions and to mitigate those threats.


Senior System Architect ISM (Industrial Scientific Medical). Responsible for Xilinx about the Industrial architectures, Dr. Corradi has 25 years of experience in semiconductors, FPGA, industrial, medical and analytic chemistry applications.

Dr. Corradi current topics of interest are motor control, power systems, power modulation, safety systems around the IEC61508 and safety networking in high performance embedded systems. For Xilinx he is a lead contributor to the IEC61508 and ISO26262 program for SIL3 certification. Before joining Xilinx he designed, managed and supervised several safety related systems in industrial and transportations applications and has been member of the steering group of several EU funded projects, SPIRE, TrainCom, EuroMain and expert in the EU project ModTrain for functional safety. He is active with the IEEE Industrial Electronics Society. Dr. Corradi belongs to the Xilinx ISM (industrial scientific medical) team and he is based in Munich (Germany).

Invited Speaker from Academia

April 16 (Wednesday), 09:00 - 10:00

David Thomas
Imperial College

Title: Doing Monte-Carlo in 5 micro-seconds: using FPGAs to go where GPUs can't


In many domains, particularly finance, FPGAs are viewed as a good solution for making low-latency decisions, such as simple message routing and the application of heuristics. For high throughput and batch-oriented numerical tasks it is assumed that GPUs or multi-core CPUs will naturally provide better overall processing power than FPGAs, due to the hardened floating-point units, large-scale parallelism, and high clock-rate. However, FPGAs have the natural advantage that very low-latency processing also implies high throughput, providing the best of both worlds.

This talk demonstrates this concept in the context of Monte-Carlo simulation, which is usually seen as a batch-oriented and numerically intensive process suitable for GPUs, and impossible to execute at micro-second time-scales. But we can exploit multiple features of an FPGA architecture to reduce latency, in particular the ability to schedule work and collect results much more quickly than any instruction based architecture. This makes it possible to do a complete numerical Monte-Carlo simulation within 5 micro-seconds (~1000 cycles), a time-scale so small that GPUs can essentially do no computation at all. So because throughput = 1/latency, the same latency-oriented FPGA architecture can also beat the GPU in terms of batch throughput.


David Thomas received his MEng in software engineering and PhD in hardware acceleration from the Dept. of Computing at Imperial College, and since 2010 has been a lecturer with the Dept. of Electrical and Electronic Engineering. His research has mainly been in the acceleration of computationally intensive applications using FPGAs and GPUs, in fields such as bio-informatics and image processing.

A particular interest is accelerating computational finance using FPGAs, where he performed much of the early academic work in numerical methods for option pricing and risk analysis, which he is now commercialising with BlueBee Technologies. He has won best paper prizes at ARC for his work in hardware accelerated Monte-Carlo simulation, and at FPL for his FPGA-optimised random number generators.

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