Description: Description: Description: Description: Description: C:\Documents and Settings\jmpc\Local Settings\Temporary Internet Files\Content.Word\logo-hipeac.png2nd Workshop on Design Tools and Architectures for Multi-Core Embedded Computing Platforms (DITAM’2013)

Berlin, Germany, January 22, 2013

To be held in conjunction with:
the
8th International Conference on High-Performance and Embedded Architectures and Compilers (HiPEAC)
January 21-23, 2013, Berlin, Germany. [Location: Radisson Blu Hotel in the center of Berlin (http://www.radissonblu.com/hotelberlin)]

[TOPICS]       [CALL FOR POSTERS/DEMOS]       [INFO TO POSTER/DEMO AUTHORS]       [WORKSHOP BOOKLET]

ORGANIZATION

OVERVIEW

FINAL PROGRAM

General Co-Chairs:

João M. P. Cardoso, Universidade do Porto, Portugal,

jmpc@acm.org

Michael Huebner, Ruhr-Universität Bochum, Germany,

Michael.Huebner@ruhr-uni-bochum.de

Run-time Adaptivity Techniques Session Chair:

Cristina Silvano, Politecnico di Milano, Italy

Heterogeneous Many-Core Architectures Session Chair:

Stephan Wong, TUDelft, The Netherlands

Design Tools and Methodologies Session Chair:

Zlatko Petrov, Honeywell, Czech Republic

Web Submissions and Poster/Demos Session Chairs:

Vittorio Zaccaria, Politecnico di Milano, Italy

Diana Goehringer, KIT, Germany

Panel Session Chair:

Michael Huebner, Ruhr-Universität Bochum, Germany

TARGET AUDIENCE

The workshop tries to bring together researchers actively working on methodologies, design tools, and architectures, for multi-core embedded computing platforms.

The workshop will have three main sessions:

l  Heterogeneous Many-Core Architectures: on the most relevant problems arising during the design exploration and optimization of heterogeneous many/multi core architectures.

l  Design Tools and Methodologies: on the state-of-the-art of tool development and on fresh ideas to make design tools aware of non-functional requirements and different target architectures.

l  Run-time Adaptivity Techniques: on the state-of-the-art techniques to dynamically manage and adapt the resources of the target architecture to runtime workloads and/or new applications.

We invite submissions of posters/demos covering the topics of the three workshop sessions. Poster submissions should either be a 150-200 word abstract or in the form of the poster itself (in an A4 or US Letter size format). Demo submissions should be a 150-200 word abstract describing the demo the authors intend to show. Both submissions should clearly identify the relevant session (Run-time Adaptivity Techniques, Heterogeneous Many-Core Architectures, or Design Tools and Methodologies).

Posters will be published online at the Workshop web site.

 

Posters/Demos submission website: http://www.easychair.org/conferences/?conf=ditam2013

 

FIRST ROUND:

Posters/Demos submission deadline: October 15, 2012

Notification of acceptance: November 15, 2012

 

SECOND ROUND:

Posters/Demos submission deadline: November 15, 2012

Notification of acceptance: December 15, 2012

Posters can be up to A0 format and preferably with a portrait layout.

Embedded computing is one of the computing areas where multi/many-core architectures are being used to achieve high-performance and/or energy savings. Tight and demanding requirements, short time-to-market and possible product upgrades, make the development of applications and the design of embedded architectures very challenging. Techniques for hardware/software co-design, for configuring the system according to application needs, for programming the multiple cores, and for generating customized hardware accelerators are currently hot topics of research. Furthermore, customization via reconfigurable hardware, run-time resource management, and run-time adaptability are seen as promising techniques to adapt the embedded computing architecture to the application requirements.

 

This workshop will serve as a privileged forum to discuss recent research and development advances from academia and industry.

 

This workshop is mainly organized around the final results of three EU funded FP7 projects, namely 2PARMA (PARallel PAradigms and Run-time MAnagement techniques for Many-core Architectures, http://www.2parma.eu/), ERA (Embedded Reconfigurable Architecture, http://www.era-project.eu/), and REFLECT (Rendering FPGAs to Multi-Core Embedded Computing, http://www.reflect-project.eu/). We plan to have contributions from other ongoing EU funded FP7 projects.

 

This workshop will present the approaches and research efforts being explored, the results achieved, and the proposed research avenues of those projects.

 

Furthermore, We intend to have three invited talks, one per main topic, given by prestigious speakers. These invited talks will possibly give other views not necessarily tied to the specific objectives of the projects. Finally, a panel will allow a fruitful discussion between members from academia and from industry.

10:00

10:10

Opening Session by General Co-Chairs: João M. P. Cardoso, Universidade do Porto, and Michael Huebner, Ruhr-Universität Bochum

10:10

10:20

Introduction to Poster/Demo Sessions: Vittorio Zaccaria , Politecnico di Milano, Italy, Diana Goehringer, KIT, Germany

10:20

12:00

Design Tools and Methodologies Session - Organizer: Zlatko Petrov, Honeywell, Czech Republic

10:20

10:50

Wayne Luk, Machine Learning for Reconfigurable Design, Imperial College London, UK

10:50

11:30

Posters Session - COFFEE BREAK, Organizers: Vittorio Zaccaria , Politecnico di Milano, Italy, Diana Goehringer, KIT, Germany

11:25

11:55

Zlatko Petrov, REFLECT: Final Achievements and Results, Honeywell, Czech Republic

12:00

13:00

Panel on: "Embedded Multi-core Computing: Challenges and Trends"

 

 

Panel Organizer and Moderator: Michael Huebner, Ruhr-Universität Bochum, Germany

 

 

Panel Members: Arnon Friedmann (Texas Instruments, USA), Ronald P. Luijten (IBM Zurich Research Laboratory, Switzerland), William Fornaciari (Politecnico di Milano, Italy), and David Bernstein (IBM Haifa Research Lab,Israel).

13:00

14:00

Lunch

14:00

15:30

Run-time Adaptivity Techniques Session - Organizer: Cristina Silvano, Politecnico di Milano, Italy

14:00

14:30

Marco Platzner, The Role of Heterogeneous Multi-cores in Self-aware Computing Systems, University of Paderborn, Paderborn, Germany

14:30

15:00

Cristina Silvano, 2PARMA: Final Achievements and Results, Politecnico di Milano, Milan, Italy

15:00

15:30

Jürgen Teich, Safe(r) Loop Computations on Multi-Cores, FAU Erlangen, Germany

15:30

16:30

Demos Session - COFFEE BREAK, Organizers: Vittorio Zaccaria , Politecnico di Milano, Italy, Diana Goehringer, KIT, Germany

16:30

18:00

Heterogeneous Many-Core Architectures Session – Organizer: Stephan Wong, TUDelft, Delft, The Netherlands

16:30

17:00

Ronald P. Luijten, The DOME Embedded 64-bit Microserver Project, IBM Zurich Research Laboratory, Zurich, Switzerland

17:00

17:30

Stephan Wong, ERA: Final Achievements and Results, TUDelft, Delft, The Netherlands

17:30

18:00

Alex Ramirez, Explicit memory hierarchy management in the ENCORE architecture, Universitat Politècnica de Catalunya and Barcelona Supercomputing Center, Barcelona, Spain

18:00

18:10

Final Wrap up

 

POSTERS SESSION [10:50-11:30]:

 

Authors and Affiliations

Title

Luigi Pomante, University of L’Aquila – DEWS, Italy

System-Level Design Space Exploration for Dedicated Heterogeneous Multi-Processor Systems

Jens Brandenburg, and Benno Stabernack, Fraunhofer Institut für Nachrichtentechnik, Germany

Performance and Memory Access Analysis for Embedded Multi-Core Media Signal Processing Platforms using NoCTrace

Simon Barner1, Jia Huang1, Andreas Raabe1, and Alois Knoll2, 1Fortiss GmbH, Germany, and 2Institut für Informatik VI, 2Technische Universität München, Germany

A Framework for Embedded System Design for MPSoCs

Thales Taborda, Gabriel Nazar, and Luigi Carro, UFRGS - Universidade Federal do Rio Grande do Sul, Brazil

Evaluating the Weighted Fault Sensitivity of the Components of a VLIW Architecture

Paulo Santos1, Gabriel Nazar1, Fakhar Anjam2, Stephan Wong2, Debora Matos1, and Luigi Carro1, 1UFRGS - Universidade Federal do Rio Grande do Sul, Brazil, 2Delft University of Technology, The Netherlands

A Fully Dynamic Reconfigurable NoC-based MPSoC: The Advantages of a Multi-Level Reconfiguration

Laszlo Bako1, Sandor-Tihamer Brassai1, Lajos Losonczi2, and Laszlo-Ferenc Marton1, 1Sapientia - Hungarian University of Transilvania, Electrical Enginnering Department, Targu-Mures, Romania, 2Lambda Communications Ltd., Romania

Multiple processor core systems on FPGA circuits implementing bio-inspired neural networks for classification tasks

Mateus Rutzig1, Antonio Carlos Schneider2, and Luigi Carro2, 1Federal University of Santa Maria, Brazil, 2UFRGS - Universidade Federal do Rio Grande do Sul, Brazil

CReAMS: An Embedded System Platform

Sandor-Tihamer Brassai1, Laszlo Bako1, Lajos Losonczi2, and Laszlo-Ferenc Marton1, 1Sapientia - Hungarian University of Transilvania, Electrical Engineering Department, Targu-Mures, Romania, 2Lambda Communications Ltd., Romania

Parallel pipeline solution for hardware implementation of artificial neural networks with in circuit real time weight update

Rabie Ben Atitallah, LAMIH, University of Valenciennes/ INRIA-Lille Nord Europe, France

HETEROGENEOUS CPU/FPGA COMPUTING SYSTEM FOR AVIONIC TEST APPLICATIONS

 

DEMOS SESSION [15:30-16:30]:

Demos and Posters about the three FP7 Projects:

-          2PARMA

-          ERA

-          REFLECT