Accelerating Big Data Systems with Reconfigurable Acceleration
Keynote Speaker: Peter Hofstee, IBM, Austin.
Abstract: This talk explores how reconfigurable logic can be leveraged in Big Data systems. We address opportunities for reconfigurable associated with storage and memory, networking, and compute. We investigate systems that process large amount of structured data, such as the IBM Netezza Data Warehousing Appliance, systems that deal with unstructured data, such as the IBM Watson system, and systems based on Apache Hadoop, and we also take look at acceleration for Apache Spark. We then look at the gene sequencing pipeline as an example of a Big Data application and discuss how several of the reconfigurable acceleration technologies we introduced earlier in the talk can be leveraged. Finally we discuss how these technologies can be leveraged in a hybrid reconfigurable (heterogeneous) cloud.
H. Peter Hofstee ( Ph.D. California Inst. of Technology, 1995 ) is a distinguished research staff member at the IBM Austin Research Laboratory, USA, and a part-time professor in Big Data Systems at Delft University of Technology, Netherlands. Peter is best known for his contributions to heterogeneous computer architecture as the chief architect of the Synergistic Processor Elements in the Cell Broadband Engine processor, used in the Sony Playstation3 and the first supercomputer to reach sustained Petaflop operation.
After returning to IBM research in 2011 he has focused on optimizing the system roadmap for big data, analytics, and cloud, including the use of accelerated compute. His early research work on coherently attached reconfigurable acceleration on Power 7 paved the way for the new coherent attach processor interface on POWER 8. Peter is an IBM master inventor with more than 100 issued patents and a member of the IBM Academy of technology.
From modern FPGA to high-level post-modern C++ abstractions for heterogeneous computing with OpenCL SYCL & SPIR-V
Keynote Speaker: Ronan Keryell, Xilinx Research Labs, Ireland.
Abstract: Modern FPGA are now huge multi-processor system-on-chips, packing around the classical FPGA reconfigurable programmable logic different kind of processors, GPU, configurable specific accelerators (video CODEC...), various hierarchies of memory and memory interfaces, configurable IO and network support, security support, power control, etc. Even the reconfigurable logic itself becomes more and more heterogeneous including specific hardware blocks such as specific DSP blocks or interconnect.
Furthermore, real applications often use several FPGA that can be used in a quite broader system, up to a full-scale data-center. So the programmer is facing now a fractal architecture, demanding also more and more control for power efficiency which tends to require a fractal set of skills and tools. Huge research efforts are attempting to solve these issues and in this talk we focus on what modern C++14 can bring, associated with the open standard SYCL pure C++-based domain-specific language and the newer SPIR-V portable low-level representation from Khronos to address programming of heterogeneous architectures.
Ronan Keryell is principal software engineer at Xilinx Research Labs working on high-level programming models for FPGA and is member of the Khronos OpenCL & SYCL C++ committee.
Ronan Keryell received his MSc in Electrical Engineering and PhD in Computer Science from École Normale Supérieure of Paris (France), on the design of a massively parallel RISC-based VLIW-SIMD graphics computer and its programming environment. He was assistant professor in the Computer Science department at MINES ParisTech and later at Télécom Bretagne (France), working on automatic parallelization, compilation of PGAS languages (High-Performance Fortran), high-level synthesis and co-design, networking and secure computing. He was co-founder of 3 start-ups, mainly in the area of High Performance Computing, and was the technical lead of the Par4All automatic parallelizer at SILKAN, targeting OpenMP, CUDA & OpenCL from sequential C & Fortran. Before joining Xilinx, he worked at AMD on programming models for GPU.