The main purpose of the HiPEAC Workshop on Reconfigurable Computing is to provide a forum for researchers active in domains within the reconfigurable computing area.

Its main focus is on reconfigurable architectures, tools and algorithms that facilitate reconfigurable systems and applications tailored for reconfigurable platforms.

The WRC’2017 forum intends to provide a substantial different event from the well-known conferences and workshops related to reconfigurable computing, by focusing on an informal way to discuss challenges, new fresh ideas, new and future trends, work in progress, etc.

The following are the planned dates for the submission and notifications of papers and posters:

  • Submission deadline: November 11, 2016
  • Extended deadline: November 21, 2016
  • Notification of acceptance: December 16, 2016

The workshop does not have formal proceedings. A selection of the papers presented at WRC'2017 will be invited to be extended and submitted to a journal special issue in IET Computers & Digital Techniques journal.

Main Topics

For the third time, the Hot Topic for WRC is HIGH-PERFORMANCE RECONFIGURABLE COMPUTING (HPRC), especially focusing:

  • Compilation, Programming Languages, and Domain-Specific Languages
  • Tools, Frameworks, Design-flows for Developing HPRC Systems
  • Virtual Machines, Middleware, and Operating Systems
  • Reconfigurable Architectures
  • Communication Infrastructures
  • Applications, including Big Data Applications
  • Runtime Adaptability
  • Resilience and Reliability
  • Performance Comparisons with other High-Performance Computing (HPC) Systems
  • Teaching HPRC

Other Topics

The other topics of interest include, but are not limited to:

Reconfigurable Architectures:

  • Novel architectures (logic blocks, interconnects, I/O)
  • Reconfigurable fabrics combined with dedicated system blocks (DSP, processors, memory etc.)
  • Memory issues: adaptivity, coherence, latency tolerance,
  • Multicore support, resource sharing support,
  • Low power reconfigurable architectures,
  • Networks on chip tailored for reconfigurable architectures,
  • Dynamic and run-time reconfiguration,
  • Defect and Fault Tolerance

Reconfigurable Tools and Technologies:

  • System level design and HW/SW co-design
  • Static and dynamic power efficiency
  • Modeling, optimization, technology mapping and design verification
  • Design and debug of reconfigurable systems
  • Testing, verification and benchmarking
  • Dedicated compilers and high-level languages
  • Operating system support for reconfigurability
  • Impact of reconfigurable hardware on real-time performance

Reconfigurable Applications and Algorithms:

  • Adaptive and bio inspired applications
  • Domain-specific applications, e.g. multimedia, bioinformatics, cryptography and more
  • High-performance, high reliability and/or power efficient application acceleration
  • Rapid prototyping