Planning of the work is divided into several tasks. There are ten main tasks, with some further divided into sub tasks. The tasks and their description are as follows:

MATLAB Implementation: Finnish the MATLAB implementation of the BM3D algorithm, that was started in the 1st semester.
Duration: 1 week.

Setup Development Environment: This task includes reading the manuals for programming and debugging the ZC706 board from Xilinx, learn to use the Vivado software and review the Verilog hardware description language.
Duration: 1 week.

System Architecture Development: Develop the system level architecture for the hardware implementation of the BM3D algorithm.
Duration: 1 week.

System Development: Development of the Verilog code for all the blocks in the system architecture, which include the matching processor, the denoising path, and all the memory and control modules.
Duration: 3 weeks.

System Simulation: Simulation in Verilog testbench of all the blocks in the system architecture, and the complete system.
Duration: 2 weeks.

Design Synthesis: System architecture synthesis in the FPGA platform, including possible error correction due to non synthesizable code.
Duration: 1.5 weeks.

Testing and Tuning on FPGA: System testing and corresponding tuning according to the results, using simulated images, i.e., images with added gaussian noise.
Duration: 1 week.

Final System Testing: Assessment of the system with real images, including performance measurements such as time of execution and PSNR (measure of image quality).
Duration: 1 week.

Optimization and improvements: Post testing optimizations of the system, if necessary and there is no delays in the planning.
Duration: 2.5 weeks.

Dissertation Writing: Writing of the dissertation that documents all the work done towards the MSc Thesis project.
Duration: 5.5 weeks.

The tasks described and the time allotted to each one are presented bellow in a Gantt Chart.