References

A list of the most relevant related work and literature used in this work can be found below:

[1] K. Dabov, A. Foi, V. Katkovnik, and K. Egiazarian. Image Denoising by Sparse 3- D Transform-Domain Collaborative Filtering. IEEE Transactions on Image Processing, 16(8):2080–2095, August 2007.

[2] Michael Elad and Michal Aharon. Image Denoising Via Sparse and Redundant Representations Over Learned Dictionaries. IEEE Transactions on Image Processing, 15(12):3736– 3745, December 2006.

[3] Qian Chen and Dapeng Wu. Image denoising by bounded block matching and 3D filtering. Signal Processing, 90(9):2778–2783, September 2010.

[4] Weisheng Dong, Lei Zhang, and Guangming Shi. Centralized sparse representation for image restoration. In 2011 International Conference on Computer Vision, pages 1259–1266. IEEE, November 2011.

[5] Weisheng Dong, Lei Zhang, Guangming Shi, and Xin Li. Nonlocally centralized sparse representation for image restoration. IEEE transactions on image processing : a publication of the IEEE Signal Processing Society, 22(4):1620–30, April 2013.

[6] K Dabov, A Foi, V Katkovnik, and K Egiazarian. BM3D image denoising with shapeadaptive principal component analysis. SPARS’09-Signal Processing . . . , 2009.

[7] Hua Zhong, Ke Ma, and Yang Zhou. Modified BM3D algorithm for image denoising using nonlocal centralization prior. Signal Processing, 106:342–347, January 2015.

[8] S.O. Memik, A.K. Katsaggelos, and M. Sarrafzadeh. Analysis and FPGA implementation of image restoration under resource constraints. IEEE Transactions on Computers, 52(3):390– 399, March 2003.

[9] G. Saldana and M. Arias-Estrada. FPGA-Based Customizable Systolic Architecture for Image Processing Applications. In 2005 International Conference on Reconfigurable Computing and FPGAs (ReConFig’05), pages 3–3. IEEE, 2005.

[10] P. Brylski and M. Strzelecki. FPGA implementation of parallel digital image processor. In Signal Processing Algorithms, Architectures, Arrangements, and Applications Conference Proceedings (SPA), 2010, pages 25–28, 2010.

[11] Stefano Di Carlo, Paolo Prinetto, Daniele Rolfo, and Pascal Trotta. AIDI: An adaptive image denoising FPGA-based IP-core for real-time applications. In 2013 NASA/ESA Conference on Adaptive Hardware and Systems (AHS-2013), pages 99–106. IEEE, June 2013.

[12] Anna Gabiger-Rose, Matthias Kube, Robert Weigel, and Richard Rose. An FPGA-Based Fully Synchronized Design of a Bilateral Filter for Real-Time Image Denoising. IEEE Transactions on Industrial Electronics, 61(8):4093–4104, August 2014.

[13] A. Aggoun and I. Jalloh. Two-dimensional DCT/IDCT architecture. IEEE Proc. - Comput. Digit. Tech., vol. 150, no. 1, p. 2, 2003.

[14] M. El Aakif, S. Belkouch, and M. M. Hassani. An efficient pipelined fast and multiplier-less 2-D IDCT for image/video decoding. In 2011 International Conference on Multimedia Computing and Systems, 2011, pp. 1–5.

Tools

The tools used during the development of the project include software and hardware and are the following:
  • MATLAB


  • Xilinx:


    • Vivado


    • Zynq 7000 ZC076 Board