Used extensively in any of the three main
test protocol steps, these basic test operations are the following:
- Apply a TCK cycle while TMS is
fixed at a pre-defined (0 or 1) logic value.
This basic test operation is required to step through the
TAP controlled state transition diagram. It will also be used to reset the
TAP controller logic (five TCK pulses while TMS=1), since many ICs do not
provide the optional /TRST pin.
- Shift a bit stream into the selected scan chain
(no comparison required on the bits shifted out). The TMS line
must be held at 0 except in the last TCK cycle, when it
must be held at 1.
There are several occasions when the bit stream shifted
out does not carry any information of interest, such as when the first
vector for interconnect test is shifted in (the values previously captured
by the BS cells are meaningless, since no test vector was previously
applied). Regardless of whether or not the bit stream shifted out is to be
compared, the last TCK cycle (shifting the last bit) has to be
applied with TMS held at 1, so that the TAP
controller leaves the Shift state with the last bit and proceeds into the
Exit1 state.
- Shift a bit stream into the selected scan chain
while the bit stream shifted out is checked against expected values in
pre-defined bit locations. Again, the TMS line must be held at 0
except in the last TCK cycle, when it must be held at 1.
During the application of a set of test vectors, and while
each new vector is shifted in (with the exception of the first), the
responses to the previous vector are shifted out. It is therefore
necessary to compare the responses being shifted out with their expected
values, but only some of the bits shifted out carry meaningful data. In
fact, and although every BS cell captures the value present in its
parallel input, only a few of those cells are associated with BS input
pins (capturing the logic values present in the PCB interconnects) or to
BS output pins where the expected value at the output of the internal IC
logic is known. For each bit to shift into the scan chain, two additional
bits are therefore required: a comparison mask (to enable or disable the
comparison) and the expected value (when known).
- Apply N TCK cycles while TMS is
held at 0.
Running BIST operations accessible through the BS
architecture requires that the TAP controller FSM is taken
to the RTI state and kept there (by maintaining TMS at 0)
during a number of TCK cycles not lower than the value specified in
the manufacturer data sheet.
- Select the BS chain in which the previous test
operations are to take place.
This basic test operation is required in the case of
multiple BS chain boards, if we assume that the test controller is able to
control only one chain at a time. |
Control
of the BS infrastructure