Concerning future work, the capability of upsampling and downsampling to YCrCb 4:2:0 formats would be an interesting addition to the features list of this module. It could be easily done using the nearest neighbor method, where it would be needed to have buffers the size of half a line in progressive mode (in 4:2:2 the number of Cb or Cr samples is half of the Y samples), or two half lines in interlaced mode. An implementation of this feature has been already done, although this feature was discarded from the features list due to the increased area it would require: the largest horizontal video active width is 4096 pixels, which means at least 2048 flip-flops in progressive mode, if implementing the buffer with a chain of registers. Using a multi-tap FIR filter to re-sample from and to 4:2:0 would impose an even larger area.

For improving the quality of the IP, the implementation of the module could be reviewed having in consideration power and area implications, which was not a goal during the development of this thesis.

Finally, one could integrate this module in a higher level design or follow the backend flow on this module, developing the place-and-route, parasitic extraction, static timing analysis and verification of the physical design, obtaining an IP ready to be produced into a physical chip.