The set of test vectors presented in table 1 was produced
by a modified "self-diagnosis" algorithm and guarantees complete
short-circuit fault detection capability. This algorithm also guarantees
that the sequence of logic values captured in any short-circuited
interconnect (the so-called STR, sequential test response) is different
from the sequence of logic values applied to any interconnect (the
so-called Sequential Test Vector, STV). For diagnostic purposes, this is
equivalent to say that *aliasing syndromes* cannot occur, since any
faulty SRV never belongs to the set of STVs. The other type of syndrome
challenging fault diagnosis occurs when disjoint sets of short-circuited
interconnects produce the same SRV. This other type is known as *confounding
syndrome* and its avoidance requires a larger number of test vectors.
`ptv[0]: 010101010001000001010101`
`ptv[1]: 010101010010000010101010`
`ptv[2]: 011010100001000001011010`
`ptv[3]: 100110100001000010100101`
`ptv[4]: 101001100010000001100110`
`ptv[5]: 101010010010000010011001`
**Table 1**: Set of test vectors generated for
short-circuit fault detection among full-BS interconnects.
The 6 horizontal test vectors shown in table 1 represent the logic
values applied *simultaneously* to the 24 interconnects of this type
(each bit stream has 24 bits) and are therefore normally referred to as
Parallel Test Vectors (PTVs). The STV applied to each interconnect may be
read in each column, starting with the STV applied to net 0 in the
leftmost column. |