Recalling that BS was developed to become an effective structural test technology for digital PCBs, it comes as no surprise that there are limited facilities available for components testing. Since the exhaustive testing approach of successively shifting in and out test stimuli and responses is unfeasible in most cases, the two alternatives remaining are the following:

• When the optional RUNBIST instruction is supported (which is essentially the case of complex VLSI devices where the overhead of BIST structures is acceptable), this instruction is used to test the component:
• The RUNBIST instruction is loaded into the instruction register.
• The minimum number of TCK cycles specified by the manufacturer should be applied while the TAP controller is kept in the RTI state.
• The BIST result is now available externally by reading the contents of the selected (by the BIST instruction) data register.
• BS components which do not support a RUNBIST instruction can only be checked "alive or dead" by the application of a reduced number of test vectors through the BS register. However, the slowness of scanning in / out each test vector / responses prevents a meaningful functional test of the internal logic except in very simple components (which in most cases will not have a BS infrastructure, except specific testability components such as TI's SCOPE octals).

It should also be referred that the IEEE 1149.1 std describes an INTEST optional instruction, meant to be used in the second situation described above, but which provides exactly the same result of the EXTEST instruction, when the BS cells are of type presented in chapter 2 (figure 2.3). Recall also that those components belonging to non-BS clusters will already have been tested during the cluster test phase, since those test vectors generated for this purpose will normally address components test as well.