Reports

Week 1:

 

Installation of the Logibone tools, installation of the Xilinx and Mentor Graphics software

Start the design of a basic project in Verilog for the Logibone.

 

Week 2:

 

Continuous of the design of a basic project in Verilog for the Logibone

Run the project designed in the Logibone

 

Week 3:

 

Study of the GPMC bus

Start of a testbench for simulating the Logibone and BeagleBone communication

Design of the website

 

Week 4:

 

Continuous of the testbench design and correction of errors in the design

Continuous of the website

 

Week 5:

 

Design of a parameterizable and easy to reconfigure register block of input and output registers

Redesign of the testbench to cover the new block test

 

Week 6:

 

Design of the memory block in a easy and reconfigurable way

 

Week 7:

 

Analyze of the possibility of having interrupts in Beaglebone from FPGA

Rearrange of the memory block position and reconfigurability for better synthesis

 

Week 8:

 

Starting adding new blocks for the project

Update website

 

Week 9:

 

Adding PWM block

Make a tool for generate the parameters

 

Week 10:

 

Continue making the tool for generate parameters

 

Week 11:

 

Adding PWM H-Bridge, UART, Digital I/O

 

Week 12:

 

Adding SPI

Upgrading the software for the new blocks

 

Week 13:

 

Adding Custom Blocks

 

Week 14:

 

Correcting bugs, updating the software tool

Correcting bugs in the hardware

 

Week 15:

 

Making a script

Develop the error system of the software tool

 

Week 16:

 

Correcting bugs

Integration of Servo Controller

 

Week 17:

 

Writing Thesis

 

Week 18:

 

Writing Thesis