The typical BS cell configuration is represented in figure 1 and shows that:
These three basic operating modes of the BS cells enable test operations to proceed according to a simple protocol which consists of the following steps:
Notice that the first and last steps described above may, and do in fact, take place at the same time, since the process of shifting in a new test vector may proceed simultaneously as the responses to the previous vector are shifted out. Notice also that the sequence of steps presented above is the same either for testing interconnects at PCB level or for testing the core logic in a BS IC. However, and since the contents of the selected scan chain have to be shifted in / out for each test vector, this test protocol becomes very slow for large numbers of test vectors. Low speed wouldnt be acceptable for testing the internal logic of an IC, which may require hundreds of thousands of vectors, but it presents no problems as far as the main application domain of BST is concerned: the structural testing of digital PCBs. As we will see later when considering the detection of open and short-circuit faults in PCB interconnects, only a reduced number of test vectors is required to enable complete fault detection.