[previous] [next] [contents]    Basic test concepts - Controllability, observability and testability

The basic procedures for the generation of test vectors to detect ss@ faults will be easier to understand if we start by considering three essential concepts in this area: controllability, observability and testability.
Controllability gives us a measure of how easy or difficult it is to force the logic level in a node to either 1 or 0. If we consider the simple circuit shown in figure 1, it is easy to verify that only 2 out of 8 possible input combinations enable us to force a 1 in node Y. On the other hand, forcing a 0 in X can be done with half of the possible input combinations, leading us to conclude that a better controllability exists in the second case.
 

Figure 1: Controllability of nodes Y=1 and X=0.

From the example above it becomes clear that low controllability in a circuit means that it will be difficult to impose the logic level in any nodes of our choice, which leads us to expect that test vector generation would be easier if it were otherwise, since:

1. As we will see later, our first step to detect a particular s@ fault consists of forcing in that node the opposite logic value
2. In an IC, the value at any node will have to be controlled only from the input pins

The same reasoning leads us to conclude that one fault can only be detected if the error signal (the difference between the value that we tried to force into the node and the actual value due to the s@ condition) can be propagated to one IC output. The observability of a node is defined precisely to give a measure of how easy or difficult it is to propagate the logic level in a node to a directly observable output. If we again consider the same circuit, now shown in figure 2, it is easy to verify that 6 out of 8 possible input combinations allow us to observe the value of Y at output F. On the other hand, observing the value of X can be done with half of the possible input combinations, leading us now to conclude that the observability of Y is better than that of X.

Figure 2: Observability of nodes Y and X

The reader may have perceived by now that the test vector generation task will be much easier for circuits with high levels of controllability and observability. In fact, it is useless to have high controllability in a node if we can not propagate its value to a circuit output; and it is just as likely useless to have high observability of a node if can not force its logic level from the circuit inputs.
To conclude this section, we will present the concept of testability as a measure of the circuit controllability and observability values in all its nodes. Obviously enough, high testability makes test vector generation much easier and will in most cases lead to better test effectiveness.