|The problem of test vector generation for combinational circuits
was satisfactorily solved long ago and many improvements on the basic D-algorithm
were introduced over the years, as well as non-deterministic alternatives,
such as various forms of pseudo-random test vector generation. However,
none of these procedures performs well with sequential circuits, because
the primary outputs are no longer a function of the primary inputs alone.
Since the same vector applied to the primary inputs can now lead to more
than one combination at the primary outputs (depending on the present state
of the circuit), our deterministic test vector generation algorithms have
to consider state information as well. Moreover, non-deterministic
procedures become nearly useless in this case, because no adequate coverage
of state transitions can be guaranteed.
The need to reach any pre-determined circuit state in a given (and small) number of clock cycles, regardless of the present state and of any ss@ faults eventually present (even those that will modify the state transition diagram), led in the mid-70s to the development of several design for test approaches, which were soon accepted as the only way of coping with the fast growing IC complexity. Various forms of scan design emerged as design for test methodologies, namely LSSD (level-sensitive scan design), which was adopted at IBM in the late 70s.
The basic idea behind scan design, as we will see in the following sections, is to enable a shift-register mode of operation for the set of flip-flops holding state information. When the circuit reverts from normal operation to test mode, all these flip-flops become a scan chain, enabling state information to be shifted in / out (regardless of the logic values present at the outputs of the combinational circuitry that normally feeds that D inputs).
Scan design and other forms of design for test approaches became widely used in industry since the late 70s and are extensively used today. However, it was not until the mid 80s that the same concepts finally found their way up in the design hierarchy, moving from IC to board level (and to system level, more recently). Scan design solutions at IC level were largely proprietary, and as such useless at board level, where ICs with incompatible design for test infrastructures were interconnected. However, and since the Joint European Test Action Group (JETAG, soon renamed JTAG when non-European companies came in) started its activity in 1985, a standard board level scan design approach quickly emerged. As a result, the IEEE 1149.1 standard boundary-scan architecture and test access port was approved in February of 1990, extending the benefits of scan design to board level and establishing a gateway to built-in self-test structures at IC level.